Logo
Explore Help
Sign In
luke/OpenRAM
Watch 1
Star 0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-30 18:02:23 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
8d7823e4dd83b6039731ef139e79765ca7950bf2
OpenRAM/technology/scn4m_subm/sp_lib
T
History
Hunter Nichols 722bc907c4 Merged with dev. Fixed conflicts in tests.
2018-12-02 23:09:00 -08:00
..
cell_1rw_1r.sp
Changed scmos bitcell 1rw,1r to have same tx widths as pbitcell.
2018-11-13 22:24:18 -08:00
cell_6t.sp
Comment spice cells. Change replica to short Q to vdd instead of Qbar to gnd.
2018-11-05 10:59:08 -08:00
dff.sp
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
replica_cell_1rw_1r.sp
Replaced bb layer with comment layer in 1rw,1r cell. Changed widths in replica cell.
2018-11-14 11:00:37 -08:00
replica_cell_6t.sp
Comment spice cells. Change replica to short Q to vdd instead of Qbar to gnd.
2018-11-05 10:59:08 -08:00
sense_amp.sp
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
tri_gate.sp
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
write_driver.sp
Replace write driver with human readable sp file.
2018-11-27 11:49:08 -08:00
Powered by Gitea Version: 1.27.2 Page: 121ms Template: 1ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API