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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 01:24:39 +02:00
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88241ca685deb70effdefd09c2e2fbb1d9154ce7
OpenRAM/technology/sky130/custom
T
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Jesse Cirimelli-Low 88241ca685 add fix for cypress sp wls
2026-04-28 17:19:54 -07:00
..
__init__.py
Use packages for imports.
2022-07-13 15:55:57 -07:00
sky130_bitcell_array.py
add fix for cypress sp wls
2026-04-28 17:19:54 -07:00
sky130_bitcell_base_array.py
squash commits
2026-04-22 01:33:47 -07:00
sky130_bitcell.py
single port fixes
2025-09-12 11:25:03 -07:00
sky130_capped_replica_bitcell_array.py
add fix for cypress sp wls
2026-04-28 17:19:54 -07:00
sky130_col_cap_array.py
singleport cba passing on both tech files
2026-03-17 14:50:43 -07:00
sky130_col_cap.py
checkpoint from tt submission
2026-01-14 12:08:26 -08:00
sky130_corner.py
Merge branch 'singleport_refactor' into array_gen
2025-02-24 23:26:28 -08:00
sky130_dummy_array.py
add fix for cypress sp wls
2026-04-28 17:19:54 -07:00
sky130_dummy_bitcell.py
Update copyright year
2023-01-28 22:56:27 -08:00
sky130_internal.py
Update copyright year
2023-01-28 22:56:27 -08:00
sky130_replica_bitcell_array.py
add fix for cypress sp wls
2026-04-28 17:19:54 -07:00
sky130_replica_bitcell.py
Update copyright year
2023-01-28 22:56:27 -08:00
sky130_replica_column.py
add fix for cypress sp wls
2026-04-28 17:19:54 -07:00
sky130_row_cap_array.py
add fix for cypress sp wls
2026-04-28 17:19:54 -07:00
sky130_row_cap.py
Update copyright year
2023-01-28 22:56:27 -08:00
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