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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 01:24:39 +02:00
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83e5848728fa95fc231aadb80d5f3888154773d7
OpenRAM/technology/freepdk45
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mrg 83e5848728 Change FreePDK and SCMOS 2rw cell to share gnd power rail.
2022-03-30 13:48:53 -07:00
..
gds_lib
Change FreePDK and SCMOS 2rw cell to share gnd power rail.
2022-03-30 13:48:53 -07:00
sim_data
Added more data for regression modules.
2021-06-21 17:21:00 -07:00
sp_lib
fix end subckt typo
2021-02-27 18:28:07 -05:00
tech
By default uniquify instances based on macro name.
2022-03-11 18:01:45 -08:00
tf
Initial klayout DRC/LVS options
2021-09-07 16:51:16 -07:00
__init__.py
FreePDK45 running with klayout and Sky130 running with magic.
2022-02-03 10:19:28 -08:00
layers.map
RELEASE 1.0
2016-11-08 09:57:35 -08:00
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