Michael Timothy Grimes 82eeb297dd Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport

2018-06-29 12:07:03 -07:00

..

base

Fix duplicate name check for some modules by checking if name is a substring. Allows pbitcell to pass.

2018-06-29 09:23:23 -07:00

characterizer

Fix module import names for python3. Rename parse function to something meaningful.

2018-06-29 09:45:07 -07:00

gdsMill

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

modules

simplfying calculations in pbitcell and changing pbitcell_array_test to check different port combinations

2018-05-31 17:39:51 -07:00

pgates

corrected gate to contact spacing

2018-05-31 18:31:34 -07:00

router

Fix unit tests to be DRC clean.

2017-06-07 10:29:53 -07:00

tests

Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport

2018-06-29 12:07:03 -07:00

verify

python 3 changes d.iterkeys() -> iter(d.keys())

2018-05-29 11:54:10 -07:00

debug.py

Clean up messages.

2018-02-02 12:31:33 -08:00

example_config_freepdk45.py

Fix num words in example.

2018-02-23 12:17:43 -08:00

example_config_scn3me_subm.py

Example config only characterizes a single corner. Remove default name of sram to generate more meaningful name. Begin pre-computed IP library.

2018-02-12 11:22:47 -08:00

gen_stimulus.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

globals.py

Allow python 3.5. Make easier to revise required version.

2018-06-29 09:23:43 -07:00

Makefile

Add Makefile for parallel test execution.

2018-01-22 13:39:07 -08:00

openram.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

options.py

Merging branch with PrivateRAM dev

2018-05-18 15:15:31 -07:00

regress.sh

Add regress.sh script for convenience

2016-11-18 08:00:34 -08:00

sram.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00