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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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7ef7c084cd54d098bbedef1ac554fb6ed67e7e10
OpenRAM/technology/scn3me_subm
T
History
Michael Timothy Grimes 0182309f92 Editting comment on rule 5.5.b in scmos tech file. Adding complimentary rule to freepdk45 tech file.
2018-08-29 14:51:50 -07:00
..
gds_lib
changed case of handmade bitcell pins from upper case to lower case. Made changes in other modules that are affected by this case. Only for SCMOS for this commit
2018-05-22 14:16:51 -07:00
mag_lib
Move sense amp to tri gate routing to M3... not ideal.
2018-04-23 09:14:18 -07:00
models
Remove KP from SCMOS models to get rid of ngspice error.
2018-03-01 11:10:04 -08:00
sp_lib
Change internal nets of 6T cell and write driver to have useful names for debugging.
2018-07-26 11:26:47 -07:00
sue_lib
RELEASE 1.0
2016-11-08 09:57:35 -08:00
tech
Editting comment on rule 5.5.b in scmos tech file. Adding complimentary rule to freepdk45 tech file.
2018-08-29 14:51:50 -07:00
tf
Add LICENSE and README from NCSU CDK
2018-03-02 10:42:23 -08:00
layers.map
RELEASE 1.0
2016-11-08 09:57:35 -08:00
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