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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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763f1e8deea8eef0169903842df1dc0255a4ae69
OpenRAM/compiler/base
T
History
Matt Guthaus 73289a6090 Clean up GdsMill. Fix rotate bug I introduced in transFlags!
2018-08-29 15:34:45 -07:00
..
contact.py
Fix analytical power of contact with new hierarchy_design level introduced.
2018-07-10 10:17:23 -07:00
design.py
Refactor banked SRAM into multiple files and dynamically load in SRAM
2018-07-10 14:17:09 -07:00
geometry.py
Update router to work with pin_layout structure.
2018-08-29 15:34:45 -07:00
hierarchy_design.py
Update router to work with pin_layout structure.
2018-08-29 15:34:45 -07:00
hierarchy_layout.py
Clean up GdsMill. Fix rotate bug I introduced in transFlags!
2018-08-29 15:34:45 -07:00
hierarchy_spice.py
Update router to work with pin_layout structure.
2018-08-29 15:34:45 -07:00
lef.py
Remove carriage returns form python files
2018-08-07 09:44:01 -07:00
path.py
…
pin_layout.py
Convert entire OpenRAM to use python3. Works with Python 3.6.
2018-05-14 16:15:45 -07:00
route.py
Update router to work with pin_layout structure.
2018-08-29 15:34:45 -07:00
utils.py
Update router to work with pin_layout structure.
2018-08-29 15:34:45 -07:00
vector.py
…
verilog.py
Move last few modules to base dir
2018-02-09 10:29:37 -08:00
wire.py
…
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