Hunter Nichols 7461f2b1bf Merged with dev.

2018-11-02 17:22:09 -07:00

..

base

Remove diagonal routing bug. Cleanup.

2018-11-02 14:57:40 -07:00

bitcells

Added replica 1rw+1r cell python modules. Also added drc/lvs checks in replica bitline, but test is failing due to pin error in freepdk45 and metal spacing error in scmos.

2018-11-01 12:29:49 -07:00

characterizer

Altered bitline with heuristic to have a larger delay chain for larger column muxes. Also have to alter the feasible period for functional tests to pass.

2018-10-30 22:19:26 -07:00

datasheet

moved flask_table warning from sram.py to datasheet_gen.py

2018-10-18 09:58:19 -07:00

drc

Moving wide metal spacing to routing grid level

2018-10-15 09:59:16 -07:00

gdsMill

Fixed merge conflicts with sram.py

2018-10-22 17:29:14 -07:00

modules

Fixed drc issues with replica bitline test.

2018-11-02 17:16:41 -07:00

pgates

Removed L shaped routing from gnd contact to wordlines in replica bitline. Corrected slight DRC errors. Optimizations to pbitcell.

2018-10-18 07:05:47 -07:00

router

Remove diagonal routing bug. Cleanup.

2018-11-02 14:57:40 -07:00

tests

Merged with dev.

2018-11-02 17:22:09 -07:00

verify

Remove old setup.tcl and edit one in tech dir

2018-10-20 15:20:15 -07:00

debug.py

Output debug warnings and errors to stderr. Clean up regress script a bit.

2018-07-11 09:51:28 -07:00

example_config_freepdk45.py

Added no mux functional test for 1rw+1r. Delay characterization also works for the custom cell as well.

2018-11-01 14:05:55 -07:00

example_config_scn4m_subm.py

Added no mux functional test for 1rw+1r. Delay characterization also works for the custom cell as well.

2018-11-01 14:05:55 -07:00

gen_stimulus.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

globals.py

Fixed merge conflicts with sram.py

2018-10-22 17:29:14 -07:00

Makefile

Add Makefile for parallel test execution.

2018-01-22 13:39:07 -08:00

openram.py

Merge branch 'dev' into supply_routing

2018-10-20 14:29:19 -07:00

options.py

Fix openram_temp directory

2018-10-06 08:08:01 -07:00

sram_1bank.py

Merge branch 'multiport' into supply_routing

2018-10-11 09:56:38 -07:00

sram_2bank.py

Cleanup some items with new sram_config. Update unit tests accordingly.

2018-09-04 10:47:24 -07:00

sram_4bank.py

Converted all submodules to use _bit notation instead of [bit]

2018-10-11 09:53:08 -07:00

sram_base.py

Altered bitline with heuristic to have a larger delay chain for larger column muxes. Also have to alter the feasible period for functional tests to pass.

2018-10-30 22:19:26 -07:00

sram_config.py

Added custom 1rw+1r bitcell. Testing are currently failing.

2018-10-22 17:02:21 -07:00

sram.py

Fixed merge conflicts with sram.py

2018-10-22 17:29:14 -07:00