OpenRAM

characterizer

Do not require hspice during tests. Check if a valid simulator is found, however.

2018-02-02 12:31:33 -08:00

gdsMill

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router

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tests

Replace LEF files with new changes.

2018-02-02 12:31:34 -08:00

verify

Change wen to en in spice lib files. Check lvs report insted of stdout with netgen.

2018-02-02 12:31:33 -08:00

bank.py

Fix pin names to lower case. Fix write driver DRC errors and LVS error.

2018-02-02 12:31:33 -08:00

bitcell_array.py

Fix pin names to lower case. Fix write driver DRC errors and LVS error.

2018-02-02 12:31:33 -08:00

bitcell.py

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contact.py

Added workaround to import layouts into Magic. Select and well layers in active contacts. Fixed missing implant enclose active DRC rule in parameterized cells.

2018-01-11 10:24:44 -08:00

control_logic.py

Fix assertion error syntax problem. Do not require hspice for functional test. Improve delay fail error message.

2018-02-02 12:31:33 -08:00

debug.py

Clean up messages.

2018-02-02 12:31:33 -08:00

delay_chain.py

Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file.

2018-01-19 16:38:19 -08:00

design.py

Fix 6T and replica cell contact spacing issues with Magic DRC.

2018-01-26 12:39:00 -08:00

example_config_freepdk45.py

Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file.

2018-01-19 16:38:19 -08:00

example_config_scn3me_subm.py

Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file.

2018-01-19 16:38:19 -08:00

geometry.py

Remove metal3 blanket blockage on library cells.

2017-12-19 09:55:59 -08:00

globals.py

Fixed command line arguments to take priority over config file. Any option can be specified in config file now.

2018-01-21 11:21:09 -08:00

hierarchical_decoder.py

Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file.

2018-01-19 16:38:19 -08:00

hierarchical_predecode2x4.py

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hierarchical_predecode3x8.py

Fix input discrepencies in pre3x8

2018-01-29 15:25:41 -08:00

hierarchical_predecode.py

Fix wrong pin order on pnand2 LVS problem.

2018-01-29 15:31:14 -08:00

hierarchy_layout.py

Add well around column muxes.

2018-02-02 12:31:33 -08:00

hierarchy_spice.py

Remove level of indirection to ptx devices to allow LVS symmetries.

2018-01-29 15:25:15 -08:00

lef.py

Remove metal3 blanket blockage on library cells.

2017-12-19 09:55:59 -08:00

Makefile

Add Makefile for parallel test execution.

2018-01-22 13:39:07 -08:00

ms_flop_array.py

Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file.

2018-01-19 16:38:19 -08:00

ms_flop.py

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openram.py

Add Makefile for parallel test execution.

2018-01-22 13:39:07 -08:00

options.py

Remove personalized temp dir.

2018-01-19 16:39:14 -08:00

path.py

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pgate.py

Fix 6T and replica cell contact spacing issues with Magic DRC.

2018-01-26 12:39:00 -08:00

pin_layout.py

Revised LEF and Verilog generation. Does not read GDS for speed improvements.

2017-12-19 09:01:24 -08:00

pinv.py

Fix 6T and replica cell contact spacing issues with Magic DRC.

2018-01-26 12:39:00 -08:00

pnand2.py

Fix wrong pin order on pnand2 LVS problem.

2018-01-29 15:31:14 -08:00

pnand3.py

Fix wrong pin order on pnand2 LVS problem.

2018-01-29 15:31:14 -08:00

pnor2.py

Fix 6T and replica cell contact spacing issues with Magic DRC.

2018-01-26 12:39:00 -08:00

precharge_array.py

Added workaround to import layouts into Magic. Select and well layers in active contacts. Fixed missing implant enclose active DRC rule in parameterized cells.

2018-01-11 10:24:44 -08:00

precharge.py

Fix precharge nwell contact spacing DRC violatin.

2018-01-26 13:53:45 -08:00

ptx.py

Remove level of indirection to ptx devices to allow LVS symmetries.

2018-01-29 15:25:00 -08:00

regress.sh

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replica_bitcell.py

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replica_bitline.py

Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file.

2018-01-19 16:38:19 -08:00

route.py

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sense_amp_array.py

Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file.

2018-01-19 16:38:19 -08:00

sense_amp.py

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single_level_column_mux_array.py

Add well around column muxes.

2018-02-02 12:31:33 -08:00

single_level_column_mux.py

Fix pwell contact in column mux to have layers for Magic.

2018-01-29 15:53:22 -08:00

sram.py

Added first test power model to sram

2018-02-02 12:31:33 -08:00

tri_gate_array.py

Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file.

2018-01-19 16:38:19 -08:00

tri_gate.py

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utils.py

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vector.py

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verilog.py

Revised LEF and Verilog generation. Does not read GDS for speed improvements.

2017-12-19 09:01:24 -08:00

wire.py

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wordline_driver.py

Fix nand input ordering to correct netgen LVS error of wordline driver.

2018-01-29 15:36:37 -08:00

write_driver_array.py

Fix pin names to lower case. Fix write driver DRC errors and LVS error.

2018-02-02 12:31:33 -08:00

write_driver.py

Fix pin names to lower case. Fix write driver DRC errors and LVS error.

2018-02-02 12:31:33 -08:00