OpenRAM

mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00

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T

Michael Timothy Grimes 64e7ed5b5e Adding pbitcell.py: a multiport bitcell with a variable number of write ports and read ports

Adding 04_pbitcell_test.py: The benchtest for pbitcell

Mostly done. Layout nearly complete with the exception of the well contacts and a connection between the gates of the read
transistors and their corresponding vias. Then several drc corrections need to be made.

2018-01-09 13:39:42 -08:00

golden

Merge update master and dev.

2017-12-18 08:13:59 -08:00

00_code_format_check_test.py

Change unit tests to use verify instead of calibre. Debugging gds read comments in magic.py.

2017-11-14 16:24:26 -08:00

01_library_drc_test.py

Change unit tests to use verify instead of calibre. Debugging gds read comments in magic.py.

2017-11-14 16:24:26 -08:00

02_library_lvs_test.py

Change unit tests to use verify instead of calibre. Debugging gds read comments in magic.py.

2017-11-14 16:24:26 -08:00

03_contact_test.py

Change unit tests to use verify instead of calibre. Debugging gds read comments in magic.py.

2017-11-14 16:24:26 -08:00

03_path_test.py

Change unit tests to use verify instead of calibre. Debugging gds read comments in magic.py.

2017-11-14 16:24:26 -08:00

03_ptx_1finger_nmos_test.py

Improve global and code structure using modules.

2017-11-16 13:52:58 -08:00

03_ptx_1finger_pmos_test.py

Change unit tests to use verify instead of calibre. Debugging gds read comments in magic.py.

2017-11-14 16:24:26 -08:00

03_ptx_3finger_nmos_test.py

Change unit tests to use verify instead of calibre. Debugging gds read comments in magic.py.

2017-11-14 16:24:26 -08:00

03_ptx_3finger_pmos_test.py

Change unit tests to use verify instead of calibre. Debugging gds read comments in magic.py.

2017-11-14 16:24:26 -08:00

03_ptx_4finger_nmos_test.py

Fix bug for even number of fingers. Add even finger tests.

2017-11-29 09:44:40 -08:00

03_ptx_4finger_pmos_test.py

Fix bug for even number of fingers. Add even finger tests.

2017-11-29 09:44:40 -08:00

03_wire_test.py

Change unit tests to use verify instead of calibre. Debugging gds read comments in magic.py.

2017-11-14 16:24:26 -08:00

04_pbitcell_test.py

Adding pbitcell.py: a multiport bitcell with a variable number of write ports and read ports

2018-01-09 13:39:42 -08:00

04_pinv_1x_beta_test.py

Reduce beta test. Remove other betas. Beta doesn't work well due to simplified rules.

2017-11-30 16:02:32 -08:00

04_pinv_1x_test.py

Split pinv unit tests.

2017-11-29 13:43:50 -08:00

04_pinv_2x_test.py

Pinv implemented, but not DRCed. More new unit tests added for pinv.

2017-11-29 16:11:15 -08:00

04_pinv_10x_test.py

Rewrite the parameterized transistor and gate classes.

2017-12-12 15:04:01 -08:00

04_pnand2_test.py

Rewrite the parameterized transistor and gate classes.

2017-12-12 15:04:01 -08:00

04_pnand3_test.py

Rewrite the parameterized transistor and gate classes.

2017-12-12 15:04:01 -08:00

04_pnor2_test.py

Rewrite the parameterized transistor and gate classes.

2017-12-12 15:04:01 -08:00

04_precharge_test.py

Rewrite the parameterized transistor and gate classes.

2017-12-12 15:04:01 -08:00

04_wordline_driver_test.py

Change unit tests to use verify instead of calibre. Debugging gds read comments in magic.py.

2017-11-14 16:24:26 -08:00

05_bitcell_array_test.py

Change unit tests to use verify instead of calibre. Debugging gds read comments in magic.py.

2017-11-14 16:24:26 -08:00

06_hierarchical_decoder_test.py

Change unit tests to use verify instead of calibre. Debugging gds read comments in magic.py.

2017-11-14 16:24:26 -08:00

06_hierarchical_predecode2x4_test.py

Change unit tests to use verify instead of calibre. Debugging gds read comments in magic.py.

2017-11-14 16:24:26 -08:00

06_hierarchical_predecode3x8_test.py

Change unit tests to use verify instead of calibre. Debugging gds read comments in magic.py.

2017-11-14 16:24:26 -08:00

07_single_level_column_mux_array_test.py

Improve global and code structure using modules.

2017-11-16 13:52:58 -08:00

08_precharge_array_test.py

Rewrite the parameterized transistor and gate classes.

2017-12-12 15:04:01 -08:00

09_sense_amp_array_test.py

Improve global and code structure using modules.

2017-11-16 13:52:58 -08:00

10_write_driver_array_test.py

Improve global and code structure using modules.

2017-11-16 13:52:58 -08:00

11_ms_flop_array_test.py

Improve global and code structure using modules.

2017-11-16 13:52:58 -08:00

12_tri_gate_array_test.py

Improve global and code structure using modules.

2017-11-16 13:52:58 -08:00

13_delay_chain_test.py

Rewrite the parameterized transistor and gate classes.

2017-12-12 15:04:01 -08:00

14_replica_bitline_test.py

Rewrite the parameterized transistor and gate classes.

2017-12-12 15:04:01 -08:00

16_control_logic_test.py

Improve global and code structure using modules.

2017-11-16 13:52:58 -08:00

19_multi_bank_test.py

Rewrite the parameterized transistor and gate classes.

2017-12-12 15:04:01 -08:00

19_single_bank_test.py

Improve global and code structure using modules.

2017-11-16 13:52:58 -08:00

20_sram_1bank_test.py

Improve global and code structure using modules.

2017-11-16 13:52:58 -08:00

20_sram_2bank_test.py

Improve global and code structure using modules.

2017-11-16 13:52:58 -08:00

20_sram_4bank_test.py

Improve global and code structure using modules.

2017-11-16 13:52:58 -08:00

21_hspice_delay_test.py

Merge update master and dev.

2017-12-18 08:13:59 -08:00

21_hspice_setuphold_test.py

Update thresholds to 15 percent. Fix ngspice data.

2017-12-15 08:01:19 -08:00

21_ngspice_delay_test.py

Merge update master and dev.

2017-12-18 08:13:59 -08:00

21_ngspice_setuphold_test.py

Update thresholds to 15 percent. Fix ngspice data.

2017-12-15 08:01:19 -08:00

22_pex_func_test_with_pinv.py

Improve output format. Rename option to be more sensible.

2017-11-22 15:57:29 -08:00

22_sram_func_test.py

Improve output format. Rename option to be more sensible.

2017-11-22 15:57:29 -08:00

23_lib_sram_model_test.py

Improve global and code structure using modules.

2017-11-16 13:52:58 -08:00

23_lib_sram_prune_test.py

Improve output format. Rename option to be more sensible.

2017-11-22 15:57:29 -08:00

23_lib_sram_test.py

Increase lib file tolerance to 25 percent.

2017-12-19 07:39:43 -08:00

24_lef_sram_test.py

Improve global and code structure using modules.

2017-11-16 13:52:58 -08:00

25_verilog_sram_test.py

Improve global and code structure using modules.

2017-11-16 13:52:58 -08:00

30_openram_test.py

Improve global and code structure using modules.

2017-11-16 13:52:58 -08:00

config_20_freepdk45.py

Improve global and code structure using modules.

2017-11-16 13:52:58 -08:00

config_20_scn3me_subm.py

Improve global and code structure using modules.

2017-11-16 13:52:58 -08:00

README

RELEASE 1.0

2016-11-08 09:57:35 -08:00

regress.py

Change some debug levels. Fix ngspice test values. ix cwd warning in some tests.

2016-11-15 08:57:06 -08:00

testutils.py

Improve global and code structure using modules.

2017-11-16 13:52:58 -08:00

README

Note that the tests turn off DRC/LVS when they perform their own check
for performance improvement. However, it must be turned back on before
the test runs an assert.