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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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5d733154e9a7a9a5b40beca427ae45ee7bcf6882
OpenRAM/compiler/base
T
History
Matt Guthaus 7b10e3bfec Convert port index lists to three simple lists.
2018-11-08 12:19:40 -08:00
..
contact.py
Update all drc usages to call function type
2018-10-12 14:37:51 -07:00
design.py
Convert port index lists to three simple lists.
2018-11-08 12:19:40 -08:00
geometry.py
Odd bug that instances were not properly rotated.
2018-10-24 16:12:27 -07:00
hierarchy_design.py
Update router to work with pin_layout structure.
2018-08-29 15:34:45 -07:00
hierarchy_layout.py
Supply router working except for off by one rail via error
2018-10-19 14:21:03 -07:00
hierarchy_spice.py
Fix print check regression
2018-10-15 13:23:31 -07:00
lef.py
Remove carriage returns form python files
2018-08-07 09:44:01 -07:00
path.py
Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev
2018-02-09 10:25:28 -08:00
pin_layout.py
Remove redundant pins in pin_group constructor. Clean up some code and comments.
2018-11-01 11:31:24 -07:00
route.py
Remove diagonal routing bug. Cleanup.
2018-11-02 14:57:40 -07:00
utils.py
Allow multiple must-connect pins with the same label.
2018-11-07 13:05:13 -08:00
vector.py
Fix Future Warning for real
2018-10-10 15:58:16 -07:00
verilog.py
Move last few modules to base dir
2018-02-09 10:29:37 -08:00
wire.py
Update all drc usages to call function type
2018-10-12 14:37:51 -07:00
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