mrg 40edbfa51f Error out on single port in sky130

2020-06-22 15:41:59 -07:00

..

bitcell_1rw_1r.py

bitcell: Remove hardcoded signal pins

2020-02-12 15:37:51 +01:00

bitcell_1w_1r.py

bitcell: Remove hardcoded signal pins

2020-02-12 15:37:51 +01:00

bitcell_base.py

…

bitcell.py

Error out on single port in sky130

2020-06-22 15:41:59 -07:00

col_cap_bitcell_1rw_1r.py

Add option for removing subckt/instances of cells for row/col caps

2020-06-22 12:35:37 -07:00

dummy_bitcell_1rw_1r.py

bitcell: Remove hardcoded signal pins

2020-02-12 15:37:51 +01:00

dummy_bitcell_1w_1r.py

bitcell: Remove hardcoded signal pins

2020-02-12 15:37:51 +01:00

dummy_bitcell.py

bitcell: Remove hardcoded signal pins

2020-02-12 15:37:51 +01:00

dummy_pbitcell.py

Add bbox for special DRC rule boundary

2019-12-05 23:14:25 +00:00

pbitcell.py

Changes to simplify metal preferred directions and pitches.

2020-05-10 11:32:45 -07:00

replica_bitcell_1rw_1r.py

bitcell: Remove hardcoded signal pins

2020-02-12 15:37:51 +01:00

replica_bitcell_1w_1r.py

bitcell: Remove hardcoded signal pins

2020-02-12 15:37:51 +01:00

replica_bitcell.py

bitcell: Remove hardcoded signal pins

2020-02-12 15:37:51 +01:00

replica_pbitcell.py

Add bbox for special DRC rule boundary

2019-12-05 23:14:25 +00:00

row_cap_bitcell_1rw_1r.py

Add option for removing subckt/instances of cells for row/col caps

2020-06-22 12:35:37 -07:00