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ThVerg
5696584608
run_script() launches the DRC/LVS scripts with
nix develop --command <script>
from a working directory of OPTS.openram_temp. nix develop resolves its
flake from the working directory, and the temp directory has no
flake.nix, so the command fails before the script ever runs:
path '/tmp/openram_<user>_<pid>_temp' does not contain a 'flake.nix', searching up
error: could not find a flake.nix file
Nothing is written to the report file, so verification then dies on the
missing output rather than on the nix error itself, which makes this
confusing to diagnose:
ERROR: file magic.py: Unable to load LVS results from
/tmp/openram_<user>_<pid>_temp/<name>.lvs.report
FileNotFoundError: [Errno 2] No such file or directory
Name the flake explicitly so it is resolved from the repository while
the script still runs in the temp directory, which the scripts depend on
for their relative copies.
Verified on a sky130 build with use_nix = True: before the change no
report is produced and the run asserts, after it both DRC and LVS run
through the devShell and write their reports.
OpenRAM
An open-source static random access memory (SRAM) compiler.
What is OpenRAM?
OpenRAM is an award winning open-source Python framework to create the layout, netlists, timing and power models, placement and routing models, and other views necessary to use SRAMs in ASIC design. OpenRAM supports integration in both commercial and open-source flows with both predictive and fabricable technologies.
Documentation
Please see our documentation and let us know if anything needs updating.
Get Involved
- Port it to a new technology
- Report bugs by submitting Github issues
- Develop new features (see how to contribute)
- Submit code/fixes using a Github pull request
- Follow our project
- Read and cite our ICCAD paper
Further Help
License
OpenRAM is licensed under the BSD 3-Clause License.
Publications
- M. R. Guthaus, J. E. Stine, S. Ataei, B. Chen, B. Wu, M. Sarwar, "OpenRAM: An Open-Source Memory Compiler," Proceedings of the 35th International Conference on Computer-Aided Design (ICCAD), 2016.
- S. Ataei, J. Stine, M. Guthaus, "A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS," International Conference on Computer Design (ICCD), 2016, pp. 499-506.
- E. Ebrahimi, M. Guthaus, J. Renau, "Timing Speculative SRAM," IEEE International Symposium on Circuits and Systems (ISCAS), 2017.
- B. Wu, J.E. Stine, M.R. Guthaus, "Fast and Area-Efficient Word-Line Optimization," IEEE International Symposium on Circuits and Systems (ISCAS), 2019.
- B. Wu, M. Guthaus, "Bottom Up Approach for High Speed SRAM Word-line Buffer Insertion Optimization," IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2019.
- H. Nichols, M. Grimes, J. Sowash, J. Cirimelli-Low, M. Guthaus "Automated Synthesis of Multi-Port Memories and Control," IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2019.
- M. Guthaus, H. Nichols, J. Cirimelli-Low, J. Kunzler, B. Wu, "Enabling Design Technology Co-Optimization of SRAMs though Open-Source Software," IEEE International Electron Devices Meeting (IEDM), 2020.
- H. Nichols, "Statistical Modeling of SRAMs," M.S. Thesis, UCSC, 2022.
Contributors & Acknowledgment
- Matthew Guthaus from VLSIDA created the OpenRAM project and is the lead architect.
- James Stine from VLSIARCH co-founded the project.
- Many students: Hunter Nichols, Michael Grimes, Jennifer Sowash, Yusu Wang, Joey Kunzler, Jesse Cirimelli-Low, Samira Ataei, Bin Wu, Brian Chen, Jeff Butera, Sage Walker
If I forgot to add you, please let me know!