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OpenRAM/compiler/tests
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jsowash 24bfaa3b76 Added write_size to test 16 and added a newline to Verilog with no wmask for test 25.
2019-07-05 15:55:03 -07:00
..
golden
Reapply jsowash update without spice model file
2019-06-24 08:59:58 -07:00
00_code_format_check_test.py
Merge branch 'pep8_cleanup' into dev
2019-06-14 08:47:10 -07:00
01_library_drc_test.py
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2019-06-14 10:13:13 -07:00
02_library_lvs_test.py
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03_contact_test.py
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03_path_test.py
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03_ptx_1finger_nmos_test.py
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03_ptx_1finger_pmos_test.py
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03_ptx_3finger_nmos_test.py
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03_ptx_3finger_pmos_test.py
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03_ptx_4finger_nmos_test.py
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03_ptx_4finger_pmos_test.py
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03_wire_test.py
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04_pand2_test.py
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04_pbitcell_test.py
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04_pbuf_test.py
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04_pdriver_test.py
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04_pinv_1x_beta_test.py
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04_pinv_1x_test.py
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04_pinv_2x_test.py
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04_pinv_10x_test.py
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04_pinvbuf_test.py
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04_pnand2_test.py
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04_pnand3_test.py
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04_pnor2_test.py
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04_precharge_test.py
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04_replica_pbitcell_test.py
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04_single_level_column_mux_test.py
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2019-06-14 10:13:13 -07:00
05_bitcell_1rw_1r_array_test.py
Merge branch 'dev' into rbl_revamp
2019-07-03 14:05:28 -07:00
05_bitcell_array_test.py
Merge branch 'dev' into rbl_revamp
2019-07-03 14:05:28 -07:00
05_dummy_array_test.py
Re-enable replica tests
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05_pbitcell_array_test.py
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2019-06-14 10:13:13 -07:00
05_replica_bitcell_array_test.py
Re-enable replica tests
2019-07-03 14:57:47 -07:00
05_replica_column_test.py
Re-enable replica tests
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06_hierarchical_decoder_test.py
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06_hierarchical_predecode2x4_test.py
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06_hierarchical_predecode3x8_test.py
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07_single_level_column_mux_array_test.py
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08_precharge_array_test.py
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08_wordline_driver_test.py
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09_sense_amp_array_test.py
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10_write_driver_array_test.py
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11_dff_array_test.py
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11_dff_buf_array_test.py
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11_dff_buf_test.py
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2019-06-14 10:13:13 -07:00
12_tri_gate_array_test.py
Merge branch 'dev' into rbl_revamp
2019-07-03 14:05:28 -07:00
13_delay_chain_test.py
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2019-06-14 10:13:13 -07:00
14_replica_bitline_multiport_test.py
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14_replica_bitline_test.py
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2019-06-14 10:13:13 -07:00
16_control_logic_multiport_test.py
Added write_size to test 16 and added a newline to Verilog with no wmask for test 25.
2019-07-05 15:55:03 -07:00
16_control_logic_test.py
Added write_size to test 16 and added a newline to Verilog with no wmask for test 25.
2019-07-05 15:55:03 -07:00
18_port_address_test.py
Create port address module
2019-07-05 09:03:52 -07:00
18_port_data_test.py
Create port address module
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19_bank_select_test.py
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19_multi_bank_test.py
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19_pmulti_bank_test.py
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19_psingle_bank_test.py
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19_single_bank_1rw_1r_test.py
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2019-06-14 10:13:13 -07:00
19_single_bank_1w_1r_test.py
New port_data module works in SCMOS
2019-07-03 13:17:12 -07:00
19_single_bank_test.py
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2019-06-14 10:13:13 -07:00
20_psram_1bank_2mux_1rw_1w_test.py
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20_psram_1bank_2mux_1w_1r_test.py
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20_psram_1bank_2mux_test.py
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20_psram_1bank_4mux_1rw_1r_test.py
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20_sram_1bank_2mux_1rw_1r_test.py
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20_sram_1bank_2mux_1w_1r_test.py
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20_sram_1bank_2mux_test.py
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20_sram_1bank_4mux_test.py
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20_sram_1bank_8mux_1rw_1r_test.py
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20_sram_1bank_8mux_test.py
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20_sram_1bank_nomux_1rw_1r_test.py
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20_sram_1bank_nomux_test.py
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20_sram_2bank_test.py
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2019-06-14 10:13:13 -07:00
21_hspice_delay_test.py
Merge branch 'dev' into rbl_revamp
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21_hspice_setuphold_test.py
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21_model_delay_test.py
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21_ngspice_delay_test.py
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21_ngspice_setuphold_test.py
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22_psram_1bank_2mux_func_test.py
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22_psram_1bank_4mux_func_test.py
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22_psram_1bank_8mux_func_test.py
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22_psram_1bank_nomux_func_test.py
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22_sram_1bank_2mux_func_test.py
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22_sram_1bank_4mux_func_test.py
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22_sram_1bank_8mux_func_test.py
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22_sram_1bank_nomux_func_test.py
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22_sram_1rw_1r_1bank_nomux_func_test.py
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23_lib_sram_model_corners_test.py
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23_lib_sram_model_test.py
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23_lib_sram_prune_test.py
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23_lib_sram_test.py
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2019-06-14 10:13:13 -07:00
24_lef_sram_test.py
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2019-06-14 10:13:13 -07:00
25_verilog_sram_test.py
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26_pex_test.py
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2019-06-14 10:13:13 -07:00
30_openram_back_end_test.py
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30_openram_front_end_test.py
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2019-06-14 10:13:13 -07:00
config_freepdk45_back_end.py
Fix space before comment
2019-06-14 08:43:41 -07:00
config_freepdk45_front_end.py
Fix space before comment
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config_freepdk45.py
Fix space before comment
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config_scn3me_subm_back_end.py
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config_scn3me_subm_front_end.py
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config_scn3me_subm.py
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config_scn4m_subm_back_end.py
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config_scn4m_subm_front_end.py
Fix space before comment
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config_scn4m_subm.py
Fix space before comment
2019-06-14 08:43:41 -07:00
regress.py
Merge branch 'pep8_cleanup' into dev
2019-06-14 08:47:10 -07:00
sram_1rw_1r_tb.v
Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench.
2019-01-11 14:15:16 -08:00
sram_1rw_tb.v
Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench.
2019-01-11 14:15:16 -08:00
sram_1rw_wmask_tb.v
Verified 1rw mask writing and changed verilog.py accordingly.
2019-07-05 15:08:59 -07:00
testutils.py
Merged and fixed conflicts with dev
2019-06-25 16:55:50 -07:00