| .. |
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and2_dec.py
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Remove add_mod and add module whenever calling add_inst.
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2021-11-22 11:33:27 -08:00 |
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and3_dec.py
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Remove add_mod and add module whenever calling add_inst.
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2021-11-22 11:33:27 -08:00 |
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and4_dec.py
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Remove add_mod and add module whenever calling add_inst.
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2021-11-22 11:33:27 -08:00 |
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bank.py
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Remove add_mod and add module whenever calling add_inst.
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2021-11-22 11:33:27 -08:00 |
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bank_select.py
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Remove add_mod and add module whenever calling add_inst.
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2021-11-22 11:33:27 -08:00 |
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bitcell_array.py
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Remove add_mod and add module whenever calling add_inst.
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2021-11-22 11:33:27 -08:00 |
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bitcell_base_array.py
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replica col lvs fix
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2021-12-15 14:19:52 -08:00 |
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col_cap_array.py
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Remove add_mod and add module whenever calling add_inst.
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2021-11-22 11:33:27 -08:00 |
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column_mux_array.py
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Fix offset to center select signal between bitlines
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2022-02-23 15:38:11 -08:00 |
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control_logic.py
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Remove add_mod and add module whenever calling add_inst.
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2021-11-22 11:33:27 -08:00 |
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delay_chain.py
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Remove add_mod and add module whenever calling add_inst.
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2021-11-22 11:33:27 -08:00 |
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dff_array.py
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Remove add_mod and add module whenever calling add_inst.
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2021-11-22 11:33:27 -08:00 |
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dff_buf.py
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Remove add_mod and add module whenever calling add_inst.
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2021-11-22 11:33:27 -08:00 |
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dff_buf_array.py
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Remove add_mod and add module whenever calling add_inst.
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2021-11-22 11:33:27 -08:00 |
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dff_inv.py
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Remove add_mod and add module whenever calling add_inst.
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2021-11-22 11:33:27 -08:00 |
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dff_inv_array.py
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Remove add_mod and add module whenever calling add_inst.
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2021-11-22 11:33:27 -08:00 |
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dummy_array.py
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Remove add_mod and add module whenever calling add_inst.
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2021-11-22 11:33:27 -08:00 |
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global_bitcell_array.py
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Remove add_mod and add module whenever calling add_inst.
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2021-11-22 11:33:27 -08:00 |
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hierarchical_decoder.py
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Don't make internal bus pins because magic will extract ports
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2022-02-23 14:06:01 -08:00 |
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hierarchical_predecode.py
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Remove add_mod and add module whenever calling add_inst.
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2021-11-22 11:33:27 -08:00 |
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hierarchical_predecode2x4.py
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Skywater changes.
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2021-03-22 15:48:14 -07:00 |
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hierarchical_predecode3x8.py
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Skywater changes.
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2021-03-22 15:48:14 -07:00 |
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hierarchical_predecode4x16.py
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Skywater changes.
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2021-03-22 15:48:14 -07:00 |
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local_bitcell_array.py
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Remove add_mod and add module whenever calling add_inst.
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2021-11-22 11:33:27 -08:00 |
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module_type.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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multibank.py
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Remove add_mod and add module whenever calling add_inst.
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2021-11-22 11:33:27 -08:00 |
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orig_bitcell_array.py
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Remove add_mod and add module whenever calling add_inst.
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2021-11-22 11:33:27 -08:00 |
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port_address.py
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Remove add_mod and add module whenever calling add_inst.
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2021-11-22 11:33:27 -08:00 |
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port_data.py
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Remove add_mod and add module whenever calling add_inst.
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2021-11-22 11:33:27 -08:00 |
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precharge_array.py
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Route horizontal supplies in write driver.
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2022-03-01 14:37:51 -08:00 |
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replica_bitcell_array.py
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Remove add_mod and add module whenever calling add_inst.
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2021-11-22 11:33:27 -08:00 |
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replica_column.py
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Route horizontal supplies in write driver.
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2022-03-01 14:37:51 -08:00 |
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row_cap_array.py
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Remove add_mod and add module whenever calling add_inst.
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2021-11-22 11:33:27 -08:00 |
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sense_amp_array.py
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Route horizontal supplies in write driver.
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2022-03-01 14:37:51 -08:00 |
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tri_gate_array.py
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Remove add_mod and add module whenever calling add_inst.
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2021-11-22 11:33:27 -08:00 |
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wordline_buffer_array.py
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Remove add_mod and add module whenever calling add_inst.
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2021-11-22 11:33:27 -08:00 |
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wordline_driver_array.py
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Remove add_mod and add module whenever calling add_inst.
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2021-11-22 11:33:27 -08:00 |
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write_driver_array.py
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Route horizontal supplies in write driver.
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2022-03-01 14:37:51 -08:00 |
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write_mask_and_array.py
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Remove add_mod and add module whenever calling add_inst.
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2021-11-22 11:33:27 -08:00 |
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