mirror of https://github.com/VLSIDA/OpenRAM.git
189 lines
6.9 KiB
Python
189 lines
6.9 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2021 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import design
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from vector import vector
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from sram_factory import factory
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from tech import cell_properties
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import debug
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from globals import OPTS
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class sense_amp_array(design.design):
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"""
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Array of sense amplifiers to read the bitlines through the column mux.
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Dynamically generated sense amp array for all bitlines.
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"""
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def __init__(self, name, word_size, words_per_row, offsets=None, num_spare_cols=None, column_offset=0):
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super().__init__(name)
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debug.info(1, "Creating {0}".format(self.name))
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self.add_comment("word_size {0}".format(word_size))
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self.add_comment("words_per_row: {0}".format(words_per_row))
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self.word_size = word_size
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self.words_per_row = words_per_row
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self.num_cols = word_size * words_per_row
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self.offsets = offsets
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if not num_spare_cols:
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self.num_spare_cols = 0
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else:
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self.num_spare_cols = num_spare_cols
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self.column_offset = column_offset
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self.row_size = self.word_size * self.words_per_row
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if OPTS.tech_name == "sky130":
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self.en_layer = "m3"
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else:
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self.en_layer = "m1"
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def get_bl_name(self):
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bl_name = "bl"
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return bl_name
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def get_br_name(self):
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br_name = "br"
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return br_name
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@property
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def data_name(self):
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return "data"
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@property
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def en_name(self):
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return "en"
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def create_netlist(self):
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self.add_modules()
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self.add_pins()
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self.create_sense_amp_array()
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def create_layout(self):
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self.place_sense_amp_array()
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self.height = self.amp.height
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self.width = self.local_insts[-1].rx()
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self.add_layout_pins()
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self.route_horizontal_pins("vdd")
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self.route_horizontal_pins("gnd")
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self.route_rails()
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self.add_boundary()
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self.DRC_LVS()
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def add_pins(self):
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for i in range(0, self.word_size + self.num_spare_cols):
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self.add_pin(self.data_name + "_{0}".format(i), "OUTPUT")
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self.add_pin(self.get_bl_name() + "_{0}".format(i), "INPUT")
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self.add_pin(self.get_br_name() + "_{0}".format(i), "INPUT")
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self.add_pin(self.en_name, "INPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def add_modules(self):
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self.amp = factory.create(module_type="sense_amp")
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# This is just used for measurements,
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# so don't add the module
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self.bitcell = factory.create(module_type=OPTS.bitcell)
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def create_sense_amp_array(self):
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self.local_insts = []
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for i in range(0, self.word_size + self.num_spare_cols):
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name = "sa_d{0}".format(i)
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self.local_insts.append(self.add_inst(name=name,
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mod=self.amp))
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self.connect_inst([self.get_bl_name() + "_{0}".format(i),
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self.get_br_name() + "_{0}".format(i),
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self.data_name + "_{0}".format(i),
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self.en_name, "vdd", "gnd"])
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def place_sense_amp_array(self):
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cell = factory.create(module_type=OPTS.bitcell)
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if(cell_properties.use_strap == True and OPTS.num_ports == 1):
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strap = factory.create(module_type=cell_properties.strap_module, version=cell_properties.strap_version)
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precharge_width = cell.width + strap.width
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else:
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precharge_width = cell.width
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if precharge_width > self.amp.width:
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self.amp_spacing = precharge_width
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else:
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self.amp_spacing = self.amp.width
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if not self.offsets:
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self.offsets = []
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for i in range(self.num_cols + self.num_spare_cols):
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self.offsets.append(i * self.amp_spacing)
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for i, xoffset in enumerate(self.offsets[0:self.num_cols:self.words_per_row]):
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if self.bitcell.mirror.y and (i * self.words_per_row + self.column_offset) % 2:
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mirror = "MY"
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xoffset = xoffset + self.amp_spacing
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else:
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mirror = ""
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amp_position = vector(xoffset, 0)
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self.local_insts[i].place(offset=amp_position, mirror=mirror)
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# place spare sense amps (will share the same enable as regular sense amps)
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for i, xoffset in enumerate(self.offsets[self.num_cols:]):
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index = self.word_size + i
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if self.bitcell.mirror.y and (index + self.column_offset) % 2:
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mirror = "MY"
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xoffset = xoffset + self.amp_spacing
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else:
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mirror = ""
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amp_position = vector(xoffset, 0)
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self.local_insts[index].place(offset=amp_position, mirror=mirror)
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def add_layout_pins(self):
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for i in range(len(self.local_insts)):
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inst = self.local_insts[i]
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bl_pin = inst.get_pin(inst.mod.get_bl_names())
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br_pin = inst.get_pin(inst.mod.get_br_names())
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dout_pin = inst.get_pin(inst.mod.dout_name)
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self.add_layout_pin(text=self.get_bl_name() + "_{0}".format(i),
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layer=bl_pin.layer,
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offset=bl_pin.ll(),
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width=bl_pin.width(),
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height=bl_pin.height())
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self.add_layout_pin(text=self.get_br_name() + "_{0}".format(i),
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layer=br_pin.layer,
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offset=br_pin.ll(),
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width=br_pin.width(),
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height=br_pin.height())
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self.add_layout_pin(text=self.data_name + "_{0}".format(i),
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layer=dout_pin.layer,
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offset=dout_pin.ll(),
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width=dout_pin.width(),
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height=dout_pin.height())
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def route_rails(self):
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# Add enable across the array
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en_pin = self.amp.get_pin(self.amp.en_name)
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start_offset = en_pin.lc().scale(0, 1)
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end_offset = start_offset + vector(self.width, 0)
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self.add_layout_pin_segment_center(text=self.en_name,
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layer=self.en_layer,
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start=start_offset,
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end=end_offset)
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for inst in self.local_insts:
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self.add_via_stack_center(from_layer=en_pin.layer,
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to_layer=self.en_layer,
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offset=inst.get_pin(self.amp.en_name).center())
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