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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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4e08e2da87643ce4be9a61e2c6bec42b15cf48ba
OpenRAM/technology/freepdk45/gds_lib
T
History
Matt Guthaus 6cdc870091 Copy 1rw/1r cell to 1w/1r.
2019-02-24 09:54:45 -08:00
..
cell_1rw_1r.gds
Re-added new width 1rw,1r bitcells with flattened gds.
2018-12-05 20:43:10 -08:00
cell_1w_1r.gds
Copy 1rw/1r cell to 1w/1r.
2019-02-24 09:54:45 -08:00
cell_6t.gds
Remove layer 230 labels from library cells
2018-11-09 11:08:20 -08:00
dff.gds
…
replica_cell_1rw_1r.gds
Re-added new width 1rw,1r bitcells with flattened gds.
2018-12-05 20:43:10 -08:00
replica_cell_1w_1r.gds
Copy 1rw/1r cell to 1w/1r.
2019-02-24 09:54:45 -08:00
replica_cell_6t.gds
Remove layer 230 labels from library cells
2018-11-09 11:12:31 -08:00
sense_amp.gds
Remove layer 230 labels from library cells
2018-11-09 11:02:19 -08:00
tri_gate.gds
Move sense amp to tri gate routing to M3... not ideal.
2018-04-23 09:14:18 -07:00
write_driver.gds
Remove layer 230 labels from library cells
2018-11-09 11:02:19 -08:00
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