mirror of https://github.com/VLSIDA/OpenRAM.git
4d3f01ff2f
There are 2 benchtests for the bitcell: 1) one with 2 write ports and 2 read ports 2) one with 2 write ports and 0 read ports The second test is meant to show how the bitcell functions when read/write ports are used instead of separate ports for read and write The bitcell currently passes both tests in both technologies Certain sizing optimizations still need to be done on the bitcell |
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| .. | ||
| base | ||
| characterizer | ||
| gdsMill | ||
| modules | ||
| pgates | ||
| router | ||
| tests | ||
| verify | ||
| Makefile | ||
| debug.py | ||
| example_config_freepdk45.py | ||
| example_config_scn3me_subm.py | ||
| gen_stimulus.py | ||
| globals.py | ||
| openram.py | ||
| options.py | ||
| pbitcell.py | ||
| regress.sh | ||
| sram.py | ||