OpenRAM/technology/sky130/modules
Jesse Cirimelli-Low 0667a93d53 single port rba passing lvs 2022-03-07 13:45:50 -08:00
..
sky130_bitcell.py
sky130_bitcell_array.py
sky130_bitcell_base_array.py
sky130_col_cap.py
sky130_col_cap_array.py
sky130_corner.py
sky130_dummy_array.py
sky130_dummy_bitcell.py
sky130_internal.py
sky130_replica_bitcell.py
sky130_replica_bitcell_array.py
sky130_replica_column.py
sky130_row_cap.py
sky130_row_cap_array.py