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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-01 18:48:10 +02:00
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41fba9d27c6f40776bef94dbbdc853e53ba104b8
OpenRAM/technology/scn3me_subm
T
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Matt Guthaus 6e332e581a Updated to include local magic rules
2018-08-15 09:46:23 -07:00
..
gds_lib
changed case of handmade bitcell pins from upper case to lower case. Made changes in other modules that are affected by this case. Only for SCMOS for this commit
2018-05-22 14:16:51 -07:00
mag_lib
Move sense amp to tri gate routing to M3... not ideal.
2018-04-23 09:14:18 -07:00
models
Remove KP from SCMOS models to get rid of ngspice error.
2018-03-01 11:10:04 -08:00
sp_lib
Change internal nets of 6T cell and write driver to have useful names for debugging.
2018-07-26 11:26:47 -07:00
sue_lib
RELEASE 1.0
2016-11-08 09:57:35 -08:00
tech
Updated to include local magic rules
2018-08-15 09:46:23 -07:00
tf
Add LICENSE and README from NCSU CDK
2018-03-02 10:42:23 -08:00
layers.map
RELEASE 1.0
2016-11-08 09:57:35 -08:00
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