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characterizer
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Improve output format. Rename option to be more sensible.
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2017-11-22 15:57:29 -08:00 |
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gdsMill
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Rewrite CONTRIBUTING.md to add changes relative to dev. Add small changes from orbe7947.
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2017-12-12 15:50:45 -08:00 |
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router
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Fix unit tests to be DRC clean.
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2017-06-07 10:29:53 -07:00 |
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tests
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Merge tolerance change from master.
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2017-12-19 09:17:43 -08:00 |
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verify
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Rewrite the parameterized transistor and gate classes.
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2017-12-12 15:04:01 -08:00 |
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bank.py
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Rewrite the parameterized transistor and gate classes.
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2017-12-12 15:04:01 -08:00 |
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bitcell.py
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Add spice pruning for speed-up. Fix spice search bugs. Add time in stages to openram output.
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2017-11-14 13:24:14 -08:00 |
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bitcell_array.py
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Change default delay modeling to analytical. Add command-line option characterization by simulation (-c).
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2017-11-09 11:13:44 -08:00 |
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contact.py
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Rewrite CONTRIBUTING.md to add changes relative to dev. Add small changes from orbe7947.
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2017-12-12 15:50:45 -08:00 |
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control_logic.py
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Revised LEF and Verilog generation. Does not read GDS for speed improvements.
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2017-12-19 09:01:24 -08:00 |
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debug.py
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Improve global and code structure using modules.
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2017-11-16 13:52:58 -08:00 |
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delay_chain.py
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Rewrite the parameterized transistor and gate classes.
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2017-12-12 15:04:01 -08:00 |
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design.py
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Rewrite the parameterized transistor and gate classes.
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2017-12-12 15:04:01 -08:00 |
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example_config_freepdk45.py
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Revised LEF and Verilog generation. Does not read GDS for speed improvements.
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2017-12-19 09:01:24 -08:00 |
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example_config_scn3me_subm.py
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Development version of new pin data structure. Tests pass LVS/DRC except for bank level.
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2017-08-23 15:02:15 -07:00 |
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geometry.py
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Revised LEF and Verilog generation. Does not read GDS for speed improvements.
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2017-12-19 09:01:24 -08:00 |
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globals.py
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Improve output format. Rename option to be more sensible.
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2017-11-22 15:57:29 -08:00 |
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hierarchical_decoder.py
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Revised LEF and Verilog generation. Does not read GDS for speed improvements.
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2017-12-19 09:01:24 -08:00 |
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hierarchical_predecode.py
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Rewrite the parameterized transistor and gate classes.
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2017-12-12 15:04:01 -08:00 |
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hierarchical_predecode2x4.py
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Change default delay modeling to analytical. Add command-line option characterization by simulation (-c).
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2017-11-09 11:13:44 -08:00 |
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hierarchical_predecode3x8.py
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Change default delay modeling to analytical. Add command-line option characterization by simulation (-c).
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2017-11-09 11:13:44 -08:00 |
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hierarchy_layout.py
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Revised LEF and Verilog generation. Does not read GDS for speed improvements.
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2017-12-19 09:01:24 -08:00 |
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hierarchy_spice.py
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Revised LEF and Verilog generation. Does not read GDS for speed improvements.
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2017-12-19 09:01:24 -08:00 |
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lef.py
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Remove tab in lef file.
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2017-12-19 09:14:59 -08:00 |
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ms_flop.py
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Change default delay modeling to analytical. Add command-line option characterization by simulation (-c).
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2017-11-09 11:13:44 -08:00 |
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ms_flop_array.py
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Change default delay modeling to analytical. Add command-line option characterization by simulation (-c).
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2017-11-09 11:13:44 -08:00 |
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openram.py
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Revised LEF and Verilog generation. Does not read GDS for speed improvements.
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2017-12-19 09:01:24 -08:00 |
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options.py
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Revised LEF and Verilog generation. Does not read GDS for speed improvements.
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2017-12-19 09:01:24 -08:00 |
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path.py
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Added pins to the ptx class. Modified pin class to do lazy write of GDS shapes to allow removal of pins.
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2017-10-05 17:35:05 -07:00 |
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pgate.py
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Rewrite the parameterized transistor and gate classes.
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2017-12-12 15:04:01 -08:00 |
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pin_layout.py
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Revised LEF and Verilog generation. Does not read GDS for speed improvements.
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2017-12-19 09:01:24 -08:00 |
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pinv.py
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Rewrite the parameterized transistor and gate classes.
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2017-12-12 15:04:01 -08:00 |
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pnand2.py
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Rewrite the parameterized transistor and gate classes.
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2017-12-12 15:04:01 -08:00 |
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pnand3.py
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Rewrite the parameterized transistor and gate classes.
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2017-12-12 15:04:01 -08:00 |
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pnor2.py
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Rewrite the parameterized transistor and gate classes.
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2017-12-12 15:04:01 -08:00 |
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precharge.py
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Revised LEF and Verilog generation. Does not read GDS for speed improvements.
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2017-12-19 09:01:24 -08:00 |
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precharge_array.py
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Revised LEF and Verilog generation. Does not read GDS for speed improvements.
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2017-12-19 09:01:24 -08:00 |
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ptx.py
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Rewrite the parameterized transistor and gate classes.
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2017-12-12 15:04:01 -08:00 |
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regress.sh
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Add regress.sh script for convenience
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2016-11-18 08:00:34 -08:00 |
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replica_bitcell.py
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Development version of new pin data structure. Tests pass LVS/DRC except for bank level.
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2017-08-23 15:02:15 -07:00 |
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replica_bitline.py
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Remove nor_2 reference
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2017-12-12 19:25:35 -08:00 |
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route.py
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Fix LEF mismatch due to path/wire hierarchy change. Add characterizer feasible delay/slew check. Update delay tests with new delays.
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2017-08-07 10:24:45 -07:00 |
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sense_amp.py
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Add spice pruning for speed-up. Fix spice search bugs. Add time in stages to openram output.
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2017-11-14 13:24:14 -08:00 |
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sense_amp_array.py
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Revised LEF and Verilog generation. Does not read GDS for speed improvements.
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2017-12-19 09:01:24 -08:00 |
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single_level_column_mux.py
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Revised LEF and Verilog generation. Does not read GDS for speed improvements.
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2017-12-19 09:01:24 -08:00 |
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single_level_column_mux_array.py
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Revised LEF and Verilog generation. Does not read GDS for speed improvements.
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2017-12-19 09:01:24 -08:00 |
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sram.py
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Revised LEF and Verilog generation. Does not read GDS for speed improvements.
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2017-12-19 09:01:24 -08:00 |
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tri_gate.py
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Add spice pruning for speed-up. Fix spice search bugs. Add time in stages to openram output.
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2017-11-14 13:24:14 -08:00 |
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tri_gate_array.py
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Change default delay modeling to analytical. Add command-line option characterization by simulation (-c).
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2017-11-09 11:13:44 -08:00 |
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utils.py
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Rewrite CONTRIBUTING.md to add changes relative to dev. Add small changes from orbe7947.
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2017-12-12 15:50:45 -08:00 |
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vector.py
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Merge master branch into router
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2017-01-09 14:04:37 -08:00 |
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verilog.py
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Revised LEF and Verilog generation. Does not read GDS for speed improvements.
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2017-12-19 09:01:24 -08:00 |
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wire.py
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Fix new offset snap problems in wordline drive. Fix ptx multifinger pin bug. Add new add_center_rect function.
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2017-10-06 15:30:15 -07:00 |
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wordline_driver.py
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Rewrite the parameterized transistor and gate classes.
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2017-12-12 15:04:01 -08:00 |
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write_driver.py
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Add spice pruning for speed-up. Fix spice search bugs. Add time in stages to openram output.
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2017-11-14 13:24:14 -08:00 |
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write_driver_array.py
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Revised LEF and Verilog generation. Does not read GDS for speed improvements.
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2017-12-19 09:01:24 -08:00 |
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