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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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3becf92e7c87e8460bafc0aa13090e18d7989ece
OpenRAM/technology/scn3me_subm
T
History
Michael Timothy Grimes 766042fe69 changed case of handmade bitcell pins from upper case to lower case. Made changes in other modules that are affected by this case. Only for SCMOS for this commit
2018-05-22 14:16:51 -07:00
..
gds_lib
changed case of handmade bitcell pins from upper case to lower case. Made changes in other modules that are affected by this case. Only for SCMOS for this commit
2018-05-22 14:16:51 -07:00
mag_lib
Move sense amp to tri gate routing to M3... not ideal.
2018-04-23 09:14:18 -07:00
models
Remove KP from SCMOS models to get rid of ngspice error.
2018-03-01 11:10:04 -08:00
sp_lib
Add dff_buf for buffered flop arrays.
2018-03-04 16:13:10 -08:00
sue_lib
RELEASE 1.0
2016-11-08 09:57:35 -08:00
tech
Single bank passing DRC and LVS again.
2018-03-23 08:13:10 -07:00
tf
Add LICENSE and README from NCSU CDK
2018-03-02 10:42:23 -08:00
layers.map
RELEASE 1.0
2016-11-08 09:57:35 -08:00
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