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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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3716030a23ab071030ef919522cbd7d47ea89bd0
OpenRAM/compiler/base
T
History
Matt Guthaus ff0a7851b7 Fix error when DRC is disabled so it doesn't initialize.
2018-11-13 17:41:32 -08:00
..
contact.py
Update all drc usages to call function type
2018-10-12 14:37:51 -07:00
design.py
Merge branch 'dev' into multiport_layout
2018-11-08 18:00:28 -08:00
geometry.py
Odd bug that instances were not properly rotated.
2018-10-24 16:12:27 -07:00
hierarchy_design.py
Fix error when DRC is disabled so it doesn't initialize.
2018-11-13 17:41:32 -08:00
hierarchy_layout.py
Change channel router to route from bottom up to simplify code.
2018-11-11 12:25:53 -08:00
hierarchy_spice.py
Fix print check regression
2018-10-15 13:23:31 -07:00
lef.py
Remove carriage returns form python files
2018-08-07 09:44:01 -07:00
path.py
Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev
2018-02-09 10:25:28 -08:00
pin_layout.py
Expand blocked pins to neighbor grid cells.
2018-11-09 14:25:10 -08:00
route.py
Remove diagonal routing bug. Cleanup.
2018-11-02 14:57:40 -07:00
utils.py
Allow multiple must-connect pins with the same label.
2018-11-07 13:05:13 -08:00
vector.py
Fix Future Warning for real
2018-10-10 15:58:16 -07:00
verilog.py
Move last few modules to base dir
2018-02-09 10:29:37 -08:00
wire.py
Update all drc usages to call function type
2018-10-12 14:37:51 -07:00
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