mrg 35c162acbd Use internal pin names in path names for signal traces.

2020-11-19 08:45:09 -08:00

..

bitcell_1port.py

Move pin name mapping to layout class.

2020-11-16 11:04:03 -08:00

bitcell_2port.py

Use internal pin names in path names for signal traces.

2020-11-19 08:45:09 -08:00

bitcell_base.py

Move pin name mapping to layout class.

2020-11-16 11:04:03 -08:00

col_cap_bitcell_2port.py

Small bug fixes related to new name mapping.

2020-11-16 13:42:42 -08:00

dummy_bitcell_1port.py

Update property settings with getters/setters

2020-11-14 08:08:42 -08:00

dummy_bitcell_2port.py

Update property settings with getters/setters

2020-11-14 08:08:42 -08:00

dummy_pbitcell.py

Refactor dynamic cell name to utilize base class

2020-11-03 13:18:46 -08:00

pbitcell.py

Fix various typos and errors

2020-11-13 16:04:07 -08:00

replica_bitcell_1port.py

Update property settings with getters/setters

2020-11-14 08:08:42 -08:00

replica_bitcell_2port.py

Small fix for finding pin names in timing graph.

2020-11-16 13:57:31 -08:00

replica_pbitcell.py

Fix bitcell and pbitcell with different cell names

2020-11-03 11:30:40 -08:00

row_cap_bitcell_2port.py

Small bug fixes related to new name mapping.

2020-11-16 13:42:42 -08:00