mrg 34c9b3a0a5 Fix well offset computation for PMOS

2020-02-03 17:37:53 +00:00

..

pand2.py

Clean up and generalize layer rules.

2019-12-17 11:03:36 -08:00

pand3.py

Clean up and generalize layer rules.

2019-12-17 11:03:36 -08:00

pbuf.py

Clean up and generalize layer rules.

2019-12-17 11:03:36 -08:00

pdriver.py

Clean up and generalize layer rules.

2019-12-17 11:03:36 -08:00

pgate.py

Pgates are 8 M1 high by default. Port data is bitcell height.

2020-01-30 03:34:04 +00:00

pinv.py

Cleanup and rename vias.

2020-01-30 01:45:33 +00:00

pinvbuf.py

Clean up and generalize layer rules.

2019-12-17 11:03:36 -08:00

pnand2.py

Cleanup and rename vias.

2020-01-30 01:45:33 +00:00

pnand3.py

Cleanup and rename vias.

2020-01-30 01:45:33 +00:00

pnor2.py

Cleanup and rename vias.

2020-01-30 01:45:33 +00:00

precharge.py

Cleanup and rename vias.

2020-01-30 01:45:33 +00:00

ptristate_inv.py

Cleanup and rename vias.

2020-01-30 01:45:33 +00:00

ptx.py

Fix well offset computation for PMOS

2020-02-03 17:37:53 +00:00

pwrite_driver.py

Add separate well design rules.

2020-01-23 19:43:41 +00:00

single_level_column_mux.py

modules: Use add_power_pin API for all modules

2020-01-28 11:47:49 +01:00