mirror of https://github.com/VLSIDA/OpenRAM.git
9749c522d1
this is the first step to allow engineers, porting technologies, more room for routing their handmade cells. For now, we don't allow the specification of power_grids where the lower layer prefers to be routed vertically. This is due to the router not connecting some pins properly in that case. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> |
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| .. | ||
| contact.py | ||
| delay_data.py | ||
| design.py | ||
| geometry.py | ||
| graph_util.py | ||
| hierarchy_design.py | ||
| hierarchy_layout.py | ||
| hierarchy_spice.py | ||
| lef.py | ||
| pin_layout.py | ||
| power_data.py | ||
| route.py | ||
| utils.py | ||
| vector.py | ||
| verilog.py | ||
| wire.py | ||
| wire_path.py | ||
| wire_spice_model.py | ||