mirror of https://github.com/VLSIDA/OpenRAM.git
183 lines
6.7 KiB
Python
183 lines
6.7 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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from hierarchy_design import hierarchy_design
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import contact
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from globals import OPTS
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import re
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class design(hierarchy_design):
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"""
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This is the same as the hierarchy_design class except it contains
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some DRC/layer constants and analytical models for other modules to reuse.
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"""
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def __init__(self, name):
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hierarchy_design.__init__(self, name)
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self.setup_drc_constants()
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self.setup_layer_constants()
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self.setup_multiport_constants()
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def setup_layer_constants(self):
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"""
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These are some layer constants used
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in many places in the compiler.
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"""
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import tech
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for key in dir(tech):
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# Single layer width rules
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match = re.match(r".*_stack$", key)
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if match:
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layer_stack = getattr(tech, key)
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# Set the stack as a local helper
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setattr(self, key, layer_stack)
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# Add the pitch
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setattr(self,
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"{}_pitch".format(layer_stack[0]),
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self.compute_pitch(layer_stack))
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if False:
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print("m1_pitch", self.m1_pitch)
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print("m2_pitch", self.m2_pitch)
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print("m3_pitch", self.m3_pitch)
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import sys
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sys.exit(1)
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def compute_pitch(self, layer_stack):
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"""
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This is contact direction independent pitch,
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i.e. we take the maximum contact dimension
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"""
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(layer1, via, layer2) = layer_stack
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contact1 = getattr(contact, layer1 + layer2)
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max_contact = max(contact1.width, contact1.height)
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layer1_space = getattr(self, layer1 + "_space")
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layer2_space = getattr(self, layer2 + "_space")
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pitch = max_contact + max(layer1_space, layer2_space)
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return pitch
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def setup_drc_constants(self):
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"""
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These are some DRC constants used in many places
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in the compiler.
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"""
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# Make some local rules for convenience
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from tech import drc
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for rule in drc.keys():
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# Single layer width rules
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match = re.search(r"minwidth_(.*)", rule)
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if match:
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if match.group(1) == "active_contact":
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setattr(self, "contact_width", drc(match.group(0)))
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else:
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setattr(self, match.group(1) + "_width", drc(match.group(0)))
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# Single layer area rules
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match = re.search(r"minarea_(.*)", rule)
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if match:
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setattr(self, match.group(0), drc(match.group(0)))
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# Single layer spacing rules
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match = re.search(r"(.*)_to_(.*)", rule)
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if match and match.group(1) == match.group(2):
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setattr(self, match.group(1) + "_space", drc(match.group(0)))
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elif match and match.group(1) != match.group(2):
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if match.group(2) == "poly_active":
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setattr(self, match.group(1) + "_to_contact",
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drc(match.group(0)))
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else:
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setattr(self, match.group(0), drc(match.group(0)))
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match = re.search(r"(.*)_enclose_(.*)", rule)
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if match:
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setattr(self, match.group(0), drc(match.group(0)))
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match = re.search(r"(.*)_extend_(.*)", rule)
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if match:
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setattr(self, match.group(0), drc(match.group(0)))
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# These are for debugging previous manual rules
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if False:
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print("poly_width", self.poly_width)
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print("poly_space", self.poly_space)
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print("m1_width", self.m1_width)
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print("m1_space", self.m1_space)
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print("m2_width", self.m2_width)
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print("m2_space", self.m2_space)
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print("m3_width", self.m3_width)
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print("m3_space", self.m3_space)
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print("m4_width", self.m4_width)
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print("m4_space", self.m4_space)
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print("active_width", self.active_width)
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print("active_space", self.active_space)
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print("contact_width", self.contact_width)
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print("poly_to_active", self.poly_to_active)
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print("poly_extend_active", self.poly_extend_active)
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print("poly_to_contact", self.poly_to_contact)
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print("contact_to_gate", self.contact_to_gate)
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print("well_enclose_active", self.well_enclose_active)
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print("implant_enclose_active", self.implant_enclose_active)
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print("implant_space", self.implant_space)
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import sys
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sys.exit(1)
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def setup_multiport_constants(self):
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"""
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These are contants and lists that aid multiport design.
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Ports are always in the order RW, W, R.
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Port indices start from 0 and increment.
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A first RW port will have clk0, csb0, web0, addr0, data0
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A first W port (with no RW ports) will be: clk0, csb0, addr0, data0
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"""
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total_ports = OPTS.num_rw_ports + OPTS.num_w_ports + OPTS.num_r_ports
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# These are the read/write port indices.
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self.readwrite_ports = []
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# These are the read/write and write-only port indices
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self.write_ports = []
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# These are the write-only port indices.
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self.writeonly_ports = []
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# These are teh read/write and read-only port indice
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self.read_ports = []
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# These are the read-only port indices.
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self.readonly_ports = []
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# These are all the ports
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self.all_ports = list(range(total_ports))
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port_number = 0
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for port in range(OPTS.num_rw_ports):
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self.readwrite_ports.append(port_number)
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self.write_ports.append(port_number)
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self.read_ports.append(port_number)
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port_number += 1
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for port in range(OPTS.num_w_ports):
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self.write_ports.append(port_number)
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self.writeonly_ports.append(port_number)
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port_number += 1
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for port in range(OPTS.num_r_ports):
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self.read_ports.append(port_number)
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self.readonly_ports.append(port_number)
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port_number += 1
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def analytical_power(self, corner, load):
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""" Get total power of a module """
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total_module_power = self.return_power()
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for inst in self.insts:
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total_module_power += inst.mod.analytical_power(corner, load)
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return total_module_power
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