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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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2e5d60ae87c02dd5ae9cfa671fb8f9220dcd4e41
OpenRAM/technology/scn3me_subm/gds_lib
T
History
Michael Timothy Grimes 766042fe69 changed case of handmade bitcell pins from upper case to lower case. Made changes in other modules that are affected by this case. Only for SCMOS for this commit
2018-05-22 14:16:51 -07:00
..
cell_6t.gds
changed case of handmade bitcell pins from upper case to lower case. Made changes in other modules that are affected by this case. Only for SCMOS for this commit
2018-05-22 14:16:51 -07:00
dff.gds
Add dff_buf for buffered flop arrays.
2018-03-04 16:13:10 -08:00
ms_flop.gds
Add M2 vias in ms_flop
2018-04-11 14:10:57 -07:00
replica_cell_6t.gds
Mostly working for 1 bank.
2018-03-23 08:14:26 -07:00
sense_amp.gds
Hand edit sense amp to have full pins rather than split from magic gds write.
2018-04-20 15:46:39 -07:00
tri_gate.gds
Move sense amp to tri gate routing to M3... not ideal.
2018-04-23 09:14:18 -07:00
write_driver.gds
Move sense amp to tri gate routing to M3... not ideal.
2018-04-23 09:14:18 -07:00
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