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golden
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Convert unit tests to scn4m_subm
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2018-09-17 11:13:46 -07:00 |
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00_code_format_check_test.py
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resolved variable name error in 00_code_format test
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2018-08-15 03:33:33 -07:00 |
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01_library_drc_test.py
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Remove extra conversion to list
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2018-07-11 12:07:37 -07:00 |
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02_library_lvs_test.py
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Fix option reload problems and checkpointing so that it works properly.
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2018-07-11 12:00:15 -07:00 |
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03_contact_test.py
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Add sketch for power grid routing code
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2018-08-29 15:34:16 -07:00 |
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03_path_test.py
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Add sketch for power grid routing code
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2018-08-29 15:34:16 -07:00 |
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03_ptx_1finger_nmos_test.py
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Add sketch for power grid routing code
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2018-08-29 15:34:16 -07:00 |
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03_ptx_1finger_pmos_test.py
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Add sketch for power grid routing code
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2018-08-29 15:34:16 -07:00 |
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03_ptx_3finger_nmos_test.py
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Add sketch for power grid routing code
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2018-08-29 15:34:16 -07:00 |
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03_ptx_3finger_pmos_test.py
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Add sketch for power grid routing code
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2018-08-29 15:34:16 -07:00 |
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03_ptx_4finger_nmos_test.py
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Add sketch for power grid routing code
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2018-08-29 15:34:16 -07:00 |
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03_ptx_4finger_pmos_test.py
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Add sketch for power grid routing code
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2018-08-29 15:34:16 -07:00 |
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03_wire_test.py
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Add sketch for power grid routing code
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2018-08-29 15:34:16 -07:00 |
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04_pbitcell_test.py
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Change options in pbitcell test to be global again.
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2018-09-05 10:59:41 -07:00 |
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04_pinv_1x_beta_test.py
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Add sketch for power grid routing code
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2018-08-29 15:34:16 -07:00 |
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04_pinv_1x_test.py
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Add sketch for power grid routing code
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2018-08-29 15:34:16 -07:00 |
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04_pinv_2x_test.py
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Add sketch for power grid routing code
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2018-08-29 15:34:16 -07:00 |
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04_pinv_10x_test.py
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Add sketch for power grid routing code
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2018-08-29 15:34:16 -07:00 |
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04_pinvbuf_test.py
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Add sketch for power grid routing code
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2018-08-29 15:34:16 -07:00 |
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04_pnand2_test.py
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Add sketch for power grid routing code
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2018-08-29 15:34:16 -07:00 |
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04_pnand3_test.py
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Add sketch for power grid routing code
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2018-08-29 15:34:16 -07:00 |
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04_pnor2_test.py
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Add sketch for power grid routing code
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2018-08-29 15:34:16 -07:00 |
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04_precharge_test.py
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Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport
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2018-09-18 18:56:15 -07:00 |
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04_replica_pbitcell_test.py
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Replacing replica_pbitcell module with a more effiecient verision. replica_pbitcell is now a wrapper for pbitcell in replica_bitcell mode.
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2018-09-13 16:53:24 -07:00 |
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04_single_level_column_mux_test.py
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Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport
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2018-09-18 18:56:15 -07:00 |
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05_bitcell_array_test.py
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Add sketch for power grid routing code
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2018-08-29 15:34:16 -07:00 |
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05_pbitcell_array_test.py
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Add sram_config class. Rename port variables for better description.
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2018-08-31 12:03:28 -07:00 |
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06_hierarchical_decoder_test.py
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Removing multiport_check option that diabled multiport portion of unit tests. Adding multiport checks to several other modules.
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2018-09-12 20:22:12 -07:00 |
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06_hierarchical_predecode2x4_test.py
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Removing multiport_check option that diabled multiport portion of unit tests. Adding multiport checks to several other modules.
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2018-09-12 20:22:12 -07:00 |
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06_hierarchical_predecode3x8_test.py
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Removing multiport_check option that diabled multiport portion of unit tests. Adding multiport checks to several other modules.
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2018-09-12 20:22:12 -07:00 |
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07_single_level_column_mux_array_test.py
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Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport
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2018-09-18 18:56:15 -07:00 |
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08_precharge_array_test.py
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Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport
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2018-09-18 18:56:15 -07:00 |
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08_wordline_driver_test.py
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Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport
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2018-09-18 18:56:15 -07:00 |
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09_sense_amp_array_test.py
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Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport
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2018-09-18 18:56:15 -07:00 |
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10_write_driver_array_test.py
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Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport
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2018-09-18 18:56:15 -07:00 |
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11_dff_array_test.py
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Add sketch for power grid routing code
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2018-08-29 15:34:16 -07:00 |
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11_dff_buf_array_test.py
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Add sketch for power grid routing code
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2018-08-29 15:34:16 -07:00 |
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11_dff_buf_test.py
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Add sketch for power grid routing code
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2018-08-29 15:34:16 -07:00 |
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11_dff_inv_array_test.py
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Add sketch for power grid routing code
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2018-08-29 15:34:16 -07:00 |
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11_dff_inv_test.py
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Add sketch for power grid routing code
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2018-08-29 15:34:16 -07:00 |
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12_tri_gate_array_test.py
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Add sketch for power grid routing code
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2018-08-29 15:34:16 -07:00 |
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13_delay_chain_test.py
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Add sketch for power grid routing code
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2018-08-29 15:34:16 -07:00 |
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14_replica_bitline_test.py
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Altering control logic for read ports and write ports, by including only read or write specific circuitry. Altering replica bitline layout to support multiport
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2018-09-25 20:00:25 -07:00 |
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16_control_logic_test.py
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Removing we_b signal from write ports since it is redundant.
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2018-10-04 09:31:04 -07:00 |
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19_bank_select_test.py
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Making changes to bank select for multiport. The height of the nor gate using pbitcell was too short and one of the contacts violated drc. Extended height of nor by drc spacing violation so it could pass in multiport.
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2018-09-27 02:01:32 -07:00 |
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19_multi_bank_test.py
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Add sram_config class. Rename port variables for better description.
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2018-08-31 12:03:28 -07:00 |
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19_pmulti_bank_test.py
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Making changes to bank select for multiport. The height of the nor gate using pbitcell was too short and one of the contacts violated drc. Extended height of nor by drc spacing violation so it could pass in multiport.
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2018-09-27 02:01:32 -07:00 |
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19_psingle_bank_test.py
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Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport
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2018-09-18 18:56:15 -07:00 |
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19_single_bank_test.py
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Add sram_config class. Rename port variables for better description.
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2018-08-31 12:03:28 -07:00 |
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20_psram_1bank_test.py
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Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport
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2018-09-18 18:56:15 -07:00 |
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20_sram_1bank_test.py
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Cleanup some items with new sram_config. Update unit tests accordingly.
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2018-09-04 10:47:24 -07:00 |
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20_sram_2bank_test.py
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Cleanup some items with new sram_config. Update unit tests accordingly.
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2018-09-04 10:47:24 -07:00 |
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20_sram_4bank_test.py
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Cleanup some items with new sram_config. Update unit tests accordingly.
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2018-09-04 10:47:24 -07:00 |
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21_hspice_delay_test.py
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Made global names for pins types. Fixed bugs in tests.
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2018-10-04 14:06:43 -07:00 |
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21_hspice_setuphold_test.py
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Convert unit tests to scn4m_subm
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2018-09-17 11:13:46 -07:00 |
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21_ngspice_delay_test.py
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Made global names for pins types. Fixed bugs in tests.
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2018-10-04 14:06:43 -07:00 |
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21_ngspice_setuphold_test.py
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Convert unit tests to scn4m_subm
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2018-09-17 11:13:46 -07:00 |
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22_hspice_psram_func_test.py
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Adding simulation.py for common functions between functional and delay tests. Updating functional test.
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2018-10-04 09:29:44 -07:00 |
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22_hspice_sram_func_test.py
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Adding simulation.py for common functions between functional and delay tests. Updating functional test.
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2018-10-04 09:29:44 -07:00 |
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22_ngspice_psram_func_test.py
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Adding simulation.py for common functions between functional and delay tests. Updating functional test.
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2018-10-04 09:29:44 -07:00 |
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22_ngspice_sram_func_test.py
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Adding simulation.py for common functions between functional and delay tests. Updating functional test.
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2018-10-04 09:29:44 -07:00 |
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23_lib_sram_model_test.py
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Cleanup some items with new sram_config. Update unit tests accordingly.
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2018-09-04 10:47:24 -07:00 |
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23_lib_sram_prune_test.py
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Cleanup some items with new sram_config. Update unit tests accordingly.
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2018-09-04 10:47:24 -07:00 |
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23_lib_sram_test.py
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Cleanup some items with new sram_config. Update unit tests accordingly.
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2018-09-04 10:47:24 -07:00 |
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24_lef_sram_test.py
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Cleanup some items with new sram_config. Update unit tests accordingly.
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2018-09-04 10:47:24 -07:00 |
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25_verilog_sram_test.py
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Cleanup some items with new sram_config. Update unit tests accordingly.
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2018-09-04 10:47:24 -07:00 |
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26_pex_test.py
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Renaming functional tests to include spice exe used. Renaming pex test to separate functional tests from pex test.
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2018-09-30 22:39:37 -07:00 |
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30_openram_test.py
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Close output log in test 30 to avoid warning
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2018-07-26 14:01:40 -07:00 |
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config_20_freepdk45.py
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Remove banks from test configs
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2018-09-24 11:41:51 -07:00 |
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config_20_scn3me_subm.py
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Remove banks from test configs
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2018-09-24 11:41:51 -07:00 |
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config_20_scn4m_subm.py
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Remove banks from test configs
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2018-09-24 11:41:51 -07:00 |
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out.log
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Add sketch for power grid routing code
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2018-08-29 15:34:16 -07:00 |
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regress.py
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Add DRC/LVS/PEX statistics in verbose=1 mode
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2018-07-11 11:59:24 -07:00 |
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sram1.gds
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Add sketch for power grid routing code
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2018-08-29 15:34:16 -07:00 |
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sram1.lef
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Add sketch for power grid routing code
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2018-08-29 15:34:16 -07:00 |
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sram1.sp
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Add sketch for power grid routing code
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2018-08-29 15:34:16 -07:00 |
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sram1_TT_5p0V_25C.lib
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Add sketch for power grid routing code
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2018-08-29 15:34:16 -07:00 |
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testutils.py
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Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport
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2018-09-18 18:56:15 -07:00 |
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