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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 01:24:39 +02:00
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2e322be7f7db96e7dc997f186227f3bca730b660
OpenRAM/compiler/characterizer
T
History
Hunter Nichols 2e322be7f7 Added changes the control logic PWL generation to match changes made in stimuli.
2018-10-04 14:09:09 -07:00
..
__init__.py
Adding simulation.py for common functions between functional and delay tests. Updating functional test.
2018-10-04 09:29:44 -07:00
charutils.py
Fix module import names for python3. Rename parse function to something meaningful.
2018-06-29 09:45:07 -07:00
delay.py
Added changes the control logic PWL generation to match changes made in stimuli.
2018-10-04 14:09:09 -07:00
functional.py
Correcting functional inheritance from simulation.
2018-10-04 13:55:59 -07:00
lib.py
Edited lib to support port indexing. Edited tests in reaction to name dict name changes. Cleaned up measurement value generation in delay.
2018-10-04 14:04:08 -07:00
setup_hold.py
Updating ms_flop removal.
2018-09-13 11:40:24 -07:00
simulation.py
Adding simulation.py for common functions between functional and delay tests. Updating functional test.
2018-10-04 09:29:44 -07:00
stimuli.py
Fixed issues with inst_sram that prevented functional test from running after merge.
2018-10-04 14:09:01 -07:00
trim_spice.py
Added regex pattern matching to trim_spice to handle multiport.
2018-10-04 14:09:09 -07:00
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