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luke
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OpenRAM
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https://github.com/VLSIDA/OpenRAM.git
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2026-08-29 17:39:02 +02:00
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2e23fffaddaaf9f304da35fc66c6772b836ed6cd
OpenRAM
/
technology
/
scn4m_subm
T
History
Jesse Cirimelli-Low
6705f99855
merge in dev
2021-05-28 14:06:23 -07:00
..
gds_lib
Rework bitcells.
2020-11-13 10:07:40 -08:00
mag_lib
Rework bitcells.
2020-11-13 10:07:40 -08:00
models
Adjusted vth0 of FF and SS models in scn4m from nominal.
2019-10-07 15:26:20 -07:00
sim_data
Removed old sim data csvs and added a new version. Added a default check for LAS in data extraction.
2021-05-24 10:44:46 -07:00
sp_lib
Rework bitcells.
2020-11-13 10:07:40 -08:00
tech
remove debug lines and merge
2021-02-09 20:53:23 -08:00
tf
Add draft lyt file -- connectivity not working
2020-08-14 10:38:22 -07:00
__init__.py
update copyright year.
2021-01-22 11:24:53 -08:00