Matt Guthaus 69261a0dc1 Routing and connecting rails with vias done. ... Refactored grid path class. Added direction enum. Does not route multi-track width wires in signal router.		2018-09-07 14:46:58 -07:00
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contact.py	Remove unique id in contact that was used for debugging	2018-09-04 16:40:52 -07:00
design.py	Refactor banked SRAM into multiple files and dynamically load in SRAM	2018-07-10 14:17:09 -07:00
geometry.py	Add back LEF blockages. Remove "absolute" flags from GDS output	2018-09-05 09:28:43 -07:00
hierarchy_design.py	Update router to work with pin_layout structure.	2018-08-29 15:34:45 -07:00
hierarchy_layout.py	Fixed bit shift amount error. Removed rotate flag for Calibre.	2018-09-04 17:27:50 -07:00
hierarchy_spice.py	Update router to work with pin_layout structure.	2018-08-29 15:34:45 -07:00
lef.py	Remove carriage returns form python files	2018-08-07 09:44:01 -07:00
path.py	Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev	2018-02-09 10:25:28 -08:00
pin_layout.py	Horizontal and vertical grid wires done.	2018-09-06 14:30:59 -07:00
route.py	Update router to work with pin_layout structure.	2018-08-29 15:34:45 -07:00
utils.py	Update router to work with pin_layout structure.	2018-08-29 15:34:45 -07:00
vector.py	Routing and connecting rails with vias done.	2018-09-07 14:46:58 -07:00
verilog.py	Move last few modules to base dir	2018-02-09 10:29:37 -08:00
wire.py	Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev	2018-02-09 10:25:28 -08:00