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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-04 08:44:12 +02:00
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2b839d34a3e22e31e8222d008816f34fe367e812
OpenRAM/technology/scn3me_subm
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Matt Guthaus 2b839d34a3 Get rid of netgen error of undefined dlatch. Fix sp_read to find correct subckt name and pins.
2018-02-27 08:59:46 -08:00
..
gds_lib
Connect dff array clk in rows and columns.
2018-02-14 16:46:26 -08:00
mag_lib
Connect dff array clk in rows and columns.
2018-02-14 16:46:26 -08:00
models
Change BSIM3 models to version 3.3.0. Add comment about multithreading selection.
2018-02-21 17:50:12 -08:00
sp_lib
Get rid of netgen error of undefined dlatch. Fix sp_read to find correct subckt name and pins.
2018-02-27 08:59:46 -08:00
sue_lib
RELEASE 1.0
2016-11-08 09:57:35 -08:00
tech
Move internal power to clock pin. Differentiate leakge power when CSb is high.
2018-02-23 12:21:32 -08:00
layers.map
RELEASE 1.0
2016-11-08 09:57:35 -08:00
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