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luke
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OpenRAM
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https://github.com/VLSIDA/OpenRAM.git
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2026-08-29 17:39:02 +02:00
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2b475670f749277e4d29cdbb2b7467e0cdab30de
OpenRAM
/
technology
/
scn4m_subm
T
History
mrg
71d86f88b0
Merge branch 'dev' into wlbuffer
2020-09-10 13:05:14 -07:00
..
gds_lib
add multiport support for pex labels
2020-01-28 00:28:55 +00:00
mag_lib
fix merge conflicts
2020-07-21 11:38:34 -07:00
models
Adjusted vth0 of FF and SS models in scn4m from nominal.
2019-10-07 15:26:20 -07:00
sp_lib
fix custom bitcell labeling; fix gds scaling in labeling
2020-01-15 09:00:02 +00:00
sue_lib
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
tech
Flatten dummy pbitcell too
2020-09-09 12:58:22 -07:00
tf
Add draft lyt file -- connectivity not working
2020-08-14 10:38:22 -07:00
__init__.py
Move DRC/LVS/PEX tools to tech file.
2019-11-29 12:01:33 -08:00