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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
Code Issues Packages Projects Releases Wiki Activity
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2a68b5721552e536fcdcbe524e27dc69841c141c
OpenRAM/compiler/router
T
History
Matt Guthaus c6f03e70d4 Convert supply to wider DRC rules
2018-12-03 11:09:17 -08:00
..
tests
Fix print check regression
2018-10-15 13:23:31 -07:00
direction.py
Remove diagonal routing bug. Cleanup.
2018-11-02 14:57:40 -07:00
grid_cell.py
Remove diagonal routing bug. Cleanup.
2018-11-02 14:57:40 -07:00
grid_path.py
Remove diagonal routing bug. Cleanup.
2018-11-02 14:57:40 -07:00
grid_utils.py
Use grid furthest from blockages when blocked pin. Enclose multiple connectors.
2018-11-19 17:32:55 -08:00
grid.py
Supply router working except for off by one rail via error
2018-10-19 14:21:03 -07:00
pin_group.py
Use grid furthest from blockages when blocked pin. Enclose multiple connectors.
2018-11-19 17:32:55 -08:00
router_tech.py
Convert supply to wider DRC rules
2018-12-03 11:09:17 -08:00
router.py
Use grid furthest from blockages when blocked pin. Enclose multiple connectors.
2018-11-19 17:32:55 -08:00
signal_grid.py
Rewrote pin enclosure code to better address off grid pins.
2018-10-10 15:15:58 -07:00
signal_router.py
Change non-preferred route costs.
2018-10-20 14:47:24 -07:00
supply_grid.py
Supply router working except:
2018-09-18 12:57:39 -07:00
supply_router.py
Convert supply to wider DRC rules
2018-12-03 11:09:17 -08:00
vector3d.py
Use grid furthest from blockages when blocked pin. Enclose multiple connectors.
2018-11-19 17:32:55 -08:00
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