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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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24bfaa3b76e889ea94bab17012c111d45ddc70a1
OpenRAM/compiler/base
T
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jsowash 24bfaa3b76 Added write_size to test 16 and added a newline to Verilog with no wmask for test 25.
2019-07-05 15:55:03 -07:00
..
contact.py
Merge branch 'pep8_cleanup' into dev
2019-06-14 08:47:10 -07:00
design.py
Merged and fixed conflicts with dev
2019-06-25 16:55:50 -07:00
geometry.py
Added functionality to express polygons in LEF files.
2019-06-25 09:20:00 -07:00
graph_util.py
Cleaned up graph additions to characterizer.
2019-06-25 16:37:35 -07:00
hierarchy_design.py
Merged and fixed conflicts with dev
2019-06-25 16:55:50 -07:00
hierarchy_layout.py
Create port address module
2019-07-05 09:03:52 -07:00
hierarchy_spice.py
fixed merge conflict
2019-07-04 11:14:32 -07:00
lef.py
Added functionality to express polygons in LEF files.
2019-06-25 09:20:00 -07:00
pin_layout.py
Fix space before comment
2019-06-14 08:43:41 -07:00
route.py
Fix space before comment
2019-06-14 08:43:41 -07:00
utils.py
Fix space before comment
2019-06-14 08:43:41 -07:00
vector.py
Fix space before comment
2019-06-14 08:43:41 -07:00
verilog.py
Added write_size to test 16 and added a newline to Verilog with no wmask for test 25.
2019-07-05 15:55:03 -07:00
wire_path.py
Fix space before comment
2019-06-14 08:43:41 -07:00
wire.py
Fix space before comment
2019-06-14 08:43:41 -07:00
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