Matt Guthaus 22d40364ec Merge branch 'multiport_cleanup' of https://github.com/VLSIDA/PrivateRAM into multiport_cleanup

2018-07-11 14:27:06 -07:00

..

base

Modify unit tests to reset options during init_openram so

2018-07-10 16:39:32 -07:00

characterizer

Fix option reload problems and checkpointing so that it works properly.

2018-07-11 12:00:15 -07:00

gdsMill

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

modules

Push create bus functions down into layout class.

2018-07-10 10:06:59 -07:00

pgates

Remove uniqe pbitcell id since it isn't needed. Convert dos EOL to unix EOL characters. Convert python2.7 to python3 in pbitcell.

2018-06-29 11:49:02 -07:00

router

Fix unit tests to be DRC clean.

2017-06-07 10:29:53 -07:00

tests

Merge branch 'multiport_cleanup' of https://github.com/VLSIDA/PrivateRAM into multiport_cleanup

2018-07-11 14:27:06 -07:00

verify

Add DRC/LVS/PEX statistics in verbose=1 mode

2018-07-11 11:59:24 -07:00

debug.py

Output debug warnings and errors to stderr. Clean up regress script a bit.

2018-07-11 09:51:28 -07:00

example_config_freepdk45.py

Fix num words in example.

2018-02-23 12:17:43 -08:00

example_config_scn3me_subm.py

Example config only characterizes a single corner. Remove default name of sram to generate more meaningful name. Begin pre-computed IP library.

2018-02-12 11:22:47 -08:00

gen_stimulus.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

globals.py

Fix order of checkpointing so that it is done after characterizer and verify have found their executables.

2018-07-11 12:12:03 -07:00

Makefile

Add Makefile for parallel test execution.

2018-01-22 13:39:07 -08:00

openram.py

Convert entire OpenRAM to use python3. Works with Python 3.6.

2018-05-14 16:15:45 -07:00

options.py

Fix options so it is in /tmp in RAM drive

2018-07-05 16:33:26 -07:00

sram_1bank.py

Refactor banked SRAM into multiple files and dynamically load in SRAM

2018-07-10 14:17:09 -07:00

sram_2bank.py

Refactor banked SRAM into multiple files and dynamically load in SRAM

2018-07-10 14:17:09 -07:00

sram_4bank.py

Refactor banked SRAM into multiple files and dynamically load in SRAM

2018-07-10 14:17:09 -07:00

sram.py

Refactor banked SRAM into multiple files and dynamically load in SRAM

2018-07-10 14:17:09 -07:00