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base
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Remove tabs
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2019-01-11 14:16:57 -08:00 |
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bitcells
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Merged with dev. Fixed conflicts in tests.
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2018-12-02 23:09:00 -08:00 |
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characterizer
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Change dout to negative clock edge relative
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2019-01-11 09:51:05 -08:00 |
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datasheet
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removed openram placeholder logo to stage for public push
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2019-01-09 12:32:17 -08:00 |
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drc
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Moving wide metal spacing to routing grid level
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2018-10-15 09:59:16 -07:00 |
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example_configs
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Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench.
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2019-01-11 14:15:16 -08:00 |
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gdsMill
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Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names.
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2018-11-16 11:48:41 -08:00 |
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modules
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Attempts to fix failing tests. Random seed differences between mada and pipeline.
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2018-12-12 13:12:26 -08:00 |
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pgates
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Removed line to skip pdriver_test
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2018-12-13 19:10:38 -08:00 |
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router
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Added router timing code. Commented combine adjacent pins due to run-time complexity
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2018-12-07 13:54:18 -08:00 |
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tests
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Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench.
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2019-01-11 14:15:16 -08:00 |
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verify
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Remove redundant DRC run in magic.
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2018-11-05 13:30:42 -08:00 |
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Makefile
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Clean up Makefile for unit tests
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2018-12-05 12:58:10 -08:00 |
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debug.py
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Output debug warnings and errors to stderr. Clean up regress script a bit.
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2018-07-11 09:51:28 -07:00 |
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gen_stimulus.py
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Convert entire OpenRAM to use python3. Works with Python 3.6.
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2018-05-14 16:15:45 -07:00 |
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git_id
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track git_id
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2018-12-05 16:13:52 -08:00 |
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globals.py
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Change kbits to bits in output
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2019-01-09 16:57:12 -08:00 |
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openram.py
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Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench.
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2019-01-11 14:15:16 -08:00 |
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options.py
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Simplifying supply router to single grid track
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2018-12-04 08:41:57 -08:00 |
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profile_stats.py
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Add profile scripts
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2018-12-07 08:56:40 -08:00 |
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run_profile.sh
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Add profile scripts
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2018-12-07 08:56:40 -08:00 |
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sram.py
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Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench.
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2019-01-11 14:15:16 -08:00 |
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sram_1bank.py
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Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench.
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2019-01-11 14:15:16 -08:00 |
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sram_2bank.py
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Cleanup some items with new sram_config. Update unit tests accordingly.
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2018-09-04 10:47:24 -07:00 |
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sram_base.py
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Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench.
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2019-01-11 14:15:16 -08:00 |
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sram_config.py
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Increase size for warning of column mux limit
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2018-12-06 13:57:38 -08:00 |
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view_profile.py
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Add profile scripts
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2018-12-07 08:56:40 -08:00 |
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