OpenRAM

golden

Update golden results for FreePDK45 tests.

2018-07-27 14:25:52 -07:00

00_code_format_check_test.py

resolved variable name error in 00_code_format test

2018-08-15 03:33:33 -07:00

01_library_drc_test.py

Remove extra conversion to list

2018-07-11 12:07:37 -07:00

02_library_lvs_test.py

Fix option reload problems and checkpointing so that it works properly.

2018-07-11 12:00:15 -07:00

03_contact_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

03_path_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

03_ptx_1finger_nmos_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

03_ptx_1finger_pmos_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

03_ptx_3finger_nmos_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

03_ptx_3finger_pmos_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

03_ptx_4finger_nmos_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

03_ptx_4finger_pmos_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

03_wire_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

04_pbitcell_test.py

Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport

2018-08-29 16:06:50 -07:00

04_pinv_1x_beta_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

04_pinv_1x_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

04_pinv_2x_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

04_pinv_10x_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

04_pinvbuf_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

04_pnand2_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

04_pnand3_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

04_pnor2_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

04_precharge_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

04_single_level_column_mux_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

05_bitcell_array_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

05_pbitcell_array_test.py

Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport

2018-08-29 16:06:50 -07:00

06_hierarchical_decoder_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

06_hierarchical_predecode2x4_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

06_hierarchical_predecode3x8_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

07_single_level_column_mux_array_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

08_precharge_array_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

08_wordline_driver_test.py

Altering wordline driver to size for any bitcell. Editting multi-port test cases for sense amp array, write driver array, and wordline driver to least number of ports as a better test of spacing betwwen amps/drivers

2018-09-03 17:31:12 -07:00

09_sense_amp_array_test.py

Altering wordline driver to size for any bitcell. Editting multi-port test cases for sense amp array, write driver array, and wordline driver to least number of ports as a better test of spacing betwwen amps/drivers

2018-09-03 17:31:12 -07:00

10_write_driver_array_test.py

Altering wordline driver to size for any bitcell. Editting multi-port test cases for sense amp array, write driver array, and wordline driver to least number of ports as a better test of spacing betwwen amps/drivers

2018-09-03 17:31:12 -07:00

11_dff_array_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

11_dff_buf_array_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

11_dff_buf_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

11_dff_inv_array_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

11_dff_inv_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

11_ms_flop_array_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

12_tri_gate_array_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

13_delay_chain_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

14_replica_bitline_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

16_control_logic_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

19_bank_select_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

19_multi_bank_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

19_psingle_bank_test.py

Skip pbitcell tests for now

2018-08-28 10:45:50 -07:00

19_single_bank_test.py

Rewrite blockage routines in router. Clean up GdsMill code.

2018-08-29 15:34:45 -07:00

20_sram_1bank_test.py

Rewrite blockage routines in router. Clean up GdsMill code.

2018-08-29 15:34:45 -07:00

20_sram_2bank_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

20_sram_4bank_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

21_hspice_delay_test.py

Update delay results with new clock routing

2018-08-14 10:51:02 -07:00

21_hspice_setuphold_test.py

Update format of delay test output during an error to directly

2018-07-26 16:05:24 -07:00

21_ngspice_delay_test.py

Update delay results with new clock routing

2018-08-14 10:51:02 -07:00

21_ngspice_setuphold_test.py

Update format of delay test output during an error to directly

2018-07-26 16:05:24 -07:00

22_pex_test.py

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

22_sram_func_test.py

Modify unit tests to reset options during init_openram so

2018-07-10 16:39:32 -07:00

23_lib_sram_model_test.py

Updated output messages in timing test comparisons.

2018-07-27 09:34:44 -07:00

23_lib_sram_prune_test.py

Updated output messages in timing test comparisons.

2018-07-27 09:34:44 -07:00

23_lib_sram_test.py

Update remaining SCMOS golden lib files.

2018-07-27 09:44:12 -07:00

24_lef_sram_test.py

Disable LEF test until supplies fixed.

2018-07-11 14:18:53 -07:00

25_verilog_sram_test.py

Modify unit tests to reset options during init_openram so

2018-07-10 16:39:32 -07:00

30_openram_test.py

Close output log in test 30 to avoid warning

2018-07-26 14:01:40 -07:00

config_20_freepdk45.py

Add multiple process corners. Unit tests use nominal corner only. Add fake SCMOS nominal models, but they are broken.

2018-02-12 09:33:23 -08:00

config_20_scn3me_subm.py

Add multiple process corners. Unit tests use nominal corner only. Add fake SCMOS nominal models, but they are broken.

2018-02-12 09:33:23 -08:00

out.log

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

regress.py

Add DRC/LVS/PEX statistics in verbose=1 mode

2018-07-11 11:59:24 -07:00

sram1_TT_5p0V_25C.lib

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

sram1.gds

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

sram1.lef

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

sram1.sp

Add sketch for power grid routing code

2018-08-29 15:34:16 -07:00

testutils.py

Update golden results for FreePDK45 tests.

2018-07-27 14:25:52 -07:00