jcirimel df4a231c04 fix merge conflicts		2020-07-21 11:38:34 -07:00
..
bitcell.py	Error out on single port in sky130	2020-06-22 15:41:59 -07:00
bitcell_1rw_1r.py	bitcell: Remove hardcoded signal pins	2020-02-12 15:37:51 +01:00
bitcell_1w_1r.py	bitcell: Remove hardcoded signal pins	2020-02-12 15:37:51 +01:00
bitcell_base.py	add multiport support for pex labels	2020-01-28 00:28:55 +00:00
col_cap_bitcell_1rw_1r.py	Add option for removing subckt/instances of cells for row/col caps	2020-06-22 12:35:37 -07:00
dummy_bitcell.py	bitcell: Remove hardcoded signal pins	2020-02-12 15:37:51 +01:00
dummy_bitcell_1rw_1r.py	bitcell: Remove hardcoded signal pins	2020-02-12 15:37:51 +01:00
dummy_bitcell_1w_1r.py	bitcell: Remove hardcoded signal pins	2020-02-12 15:37:51 +01:00
dummy_pbitcell.py	Add bbox for special DRC rule boundary	2019-12-05 23:14:25 +00:00
pbitcell.py	fix merge conflicts	2020-07-21 11:38:34 -07:00
replica_bitcell.py	bitcell: Remove hardcoded signal pins	2020-02-12 15:37:51 +01:00
replica_bitcell_1rw_1r.py	bitcell: Remove hardcoded signal pins	2020-02-12 15:37:51 +01:00
replica_bitcell_1w_1r.py	bitcell: Remove hardcoded signal pins	2020-02-12 15:37:51 +01:00
replica_pbitcell.py	Add bbox for special DRC rule boundary	2019-12-05 23:14:25 +00:00
row_cap_bitcell_1rw_1r.py	Add option for removing subckt/instances of cells for row/col caps	2020-06-22 12:35:37 -07:00