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base
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Improve comments. Simplify function interface for channel route.
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2018-09-11 15:53:12 -07:00 |
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characterizer
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Corrections to functional test that adds multiple cs_b signals per port
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2018-09-21 09:59:44 -07:00 |
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gdsMill
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Add back LEF blockages. Remove "absolute" flags from GDS output
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2018-09-05 09:28:43 -07:00 |
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modules
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Editting top level netlist for multiport. Now there are multiple control logic modules, one per port. Since diffent ports are driven by different clocks, also separating dff modules, one per port.
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2018-09-26 19:10:24 -07:00 |
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pgates
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Replacing replica_pbitcell module with a more effiecient verision. replica_pbitcell is now a wrapper for pbitcell in replica_bitcell mode.
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2018-09-13 16:53:24 -07:00 |
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router
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Add inflate blockages and remove pins from blockages.
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2018-09-05 11:06:17 -07:00 |
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tests
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Altering bank select for port specific use. Altering bank select test to test different port types. Altering bank for control signal changes.
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2018-09-26 14:53:55 -07:00 |
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verify
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Hard code flatten commands for the unique id precharge array
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2018-09-13 15:15:41 -07:00 |
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Makefile
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Add Makefile for parallel test execution.
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2018-01-22 13:39:07 -08:00 |
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debug.py
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Output debug warnings and errors to stderr. Clean up regress script a bit.
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2018-07-11 09:51:28 -07:00 |
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example_config_freepdk45.py
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Merge branch 'dev' into multiport_characterization
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2018-08-29 01:27:37 -07:00 |
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example_config_scn3me_subm.py
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Changed power logic in lib file writing. Syntax incorrect still for multiport. To be changed when top-level is done.
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2018-09-10 19:33:59 -07:00 |
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gen_stimulus.py
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Convert entire OpenRAM to use python3. Works with Python 3.6.
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2018-05-14 16:15:45 -07:00 |
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globals.py
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Change default to scn4m
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2018-09-13 15:26:03 -07:00 |
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openram.py
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Cleanup some items with new sram_config. Update unit tests accordingly.
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2018-09-04 10:47:24 -07:00 |
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options.py
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Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport
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2018-09-18 18:56:15 -07:00 |
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sram.py
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Cleanup some items with new sram_config. Update unit tests accordingly.
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2018-09-04 10:47:24 -07:00 |
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sram_1bank.py
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Editting top level netlist for multiport. Now there are multiple control logic modules, one per port. Since diffent ports are driven by different clocks, also separating dff modules, one per port.
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2018-09-26 19:10:24 -07:00 |
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sram_2bank.py
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Cleanup some items with new sram_config. Update unit tests accordingly.
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2018-09-04 10:47:24 -07:00 |
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sram_4bank.py
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Cleanup some items with new sram_config. Update unit tests accordingly.
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2018-09-04 10:47:24 -07:00 |
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sram_base.py
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Editting top level netlist for multiport. Now there are multiple control logic modules, one per port. Since diffent ports are driven by different clocks, also separating dff modules, one per port.
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2018-09-26 19:10:24 -07:00 |
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sram_config.py
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Cleanup some items with new sram_config. Update unit tests accordingly.
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2018-09-04 10:47:24 -07:00 |
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