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bank.py
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Fix unattached label on sense amp out by changing layer.
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2018-04-20 15:48:38 -07:00 |
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bank_select.py
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Supply to M3 for bank select logic
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2018-04-11 16:55:09 -07:00 |
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bitcell.py
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Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
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2018-03-01 23:34:15 -08:00 |
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bitcell_array.py
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Mostly working for 1 bank.
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2018-03-23 08:14:26 -07:00 |
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control_logic.py
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Change stages of delay to odd
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2018-04-16 10:15:15 -07:00 |
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delay_chain.py
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Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control.
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2018-03-23 08:14:09 -07:00 |
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dff.py
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Add dff_buf for buffered flop arrays.
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2018-03-04 16:13:10 -08:00 |
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dff_array.py
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Reworking control logic for veritcal poly. Rewrote delay line. Rewrote buffered-DFF array.
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2018-03-23 08:12:47 -07:00 |
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dff_buf.py
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Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control.
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2018-03-23 08:14:09 -07:00 |
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dff_buf_array.py
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Add M3 pins on dff_buf array
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2018-04-11 12:09:15 -07:00 |
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dff_inv.py
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Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control.
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2018-03-23 08:14:09 -07:00 |
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dff_inv_array.py
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Add bank_sel to bank_select module as input.
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2018-03-23 08:13:39 -07:00 |
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hierarchical_decoder.py
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Remove supply rails in decoder
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2018-04-16 15:59:52 -07:00 |
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hierarchical_predecode.py
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Remove dead logic
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2018-04-11 16:54:55 -07:00 |
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hierarchical_predecode2x4.py
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First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.
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2018-02-26 16:32:28 -08:00 |
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hierarchical_predecode3x8.py
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First version of analytical power models. Still huge room for improvement. Analytical power printed with 1 verbose level.
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2018-02-26 16:32:28 -08:00 |
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ms_flop.py
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Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
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2018-03-01 23:34:15 -08:00 |
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ms_flop_array.py
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Fix ms_flop array for M3 supplies
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2018-04-11 14:25:04 -07:00 |
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precharge_array.py
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Route precharge_array vdd in M3
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2018-04-04 13:49:55 -07:00 |
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replica_bitcell.py
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Organize top-level files into subdirs.
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2018-02-09 10:25:24 -08:00 |
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replica_bitline.py
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Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control.
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2018-03-23 08:14:09 -07:00 |
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sense_amp.py
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Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
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2018-03-01 23:34:15 -08:00 |
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sense_amp_array.py
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Fix some errors
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2018-04-18 09:37:33 -07:00 |
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single_level_column_mux_array.py
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Move precharge and column mux cells to pgate directory.
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2018-04-06 17:15:14 -07:00 |
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tri_gate.py
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Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
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2018-03-01 23:34:15 -08:00 |
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tri_gate_array.py
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Tri gate and array supply to M2 and M3
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2018-04-11 15:11:47 -07:00 |
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wordline_driver.py
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Move supply to M3 in wordline driver
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2018-04-11 16:23:45 -07:00 |
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write_driver.py
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Organize top-level files into subdirs.
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2018-02-09 10:25:24 -08:00 |
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write_driver_array.py
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Remove m2 from write driver
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2018-04-16 16:15:35 -07:00 |
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