Hunter Nichols 178d3df5f5 Added graph to characterizer to get net names and perform s_en checks. Graph not working with column mux.

2019-05-14 14:44:49 -07:00

..

bank_select.py

First draft of sram_factory code

2019-01-16 16:15:38 -08:00

bank.py

Added graph creation and functions in base class and lower level modules.

2019-04-24 14:23:22 -07:00

bitcell_array.py

Added graph creation and functions in base class and lower level modules.

2019-04-24 14:23:22 -07:00

control_logic.py

Cleaned up names, added exclusions to narrow paths for analysis.

2019-04-24 23:51:09 -07:00

delay_chain.py

Added some comments to the spice files.

2019-01-25 15:00:00 -08:00

dff_array.py

Added linear corner factors in analytical delay model.

2019-03-04 00:42:18 -08:00

dff_buf_array.py

Added linear corner factors in analytical delay model.

2019-03-04 00:42:18 -08:00

dff_buf.py

Added linear corner factors in analytical delay model.

2019-03-04 00:42:18 -08:00

dff_inv_array.py

Added linear corner factors in analytical delay model.

2019-03-04 00:42:18 -08:00

dff_inv.py

Added linear corner factors in analytical delay model.

2019-03-04 00:42:18 -08:00

dff.py

Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based.

2019-05-07 00:52:27 -07:00

hierarchical_decoder.py

Added graph creation and functions in base class and lower level modules.

2019-04-24 14:23:22 -07:00

hierarchical_predecode2x4.py

Added linear corner factors in analytical delay model.

2019-03-04 00:42:18 -08:00

hierarchical_predecode3x8.py

Added linear corner factors in analytical delay model.

2019-03-04 00:42:18 -08:00

hierarchical_predecode.py

First draft of sram_factory code

2019-01-16 16:15:38 -08:00

multibank.py

Added linear corner factors in analytical delay model.

2019-03-04 00:42:18 -08:00

precharge_array.py

Added graph creation and functions in base class and lower level modules.

2019-04-24 14:23:22 -07:00

replica_bitline.py

Change pbuf/pinv to pdriver in control logic.

2019-01-23 12:03:52 -08:00

sense_amp_array.py

Added more accurate bitline delay capacitance estimations

2019-04-09 01:56:32 -07:00

sense_amp.py

Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based.

2019-05-07 00:52:27 -07:00

single_level_column_mux_array.py

Added more accurate bitline delay capacitance estimations

2019-04-09 01:56:32 -07:00

tri_gate_array.py

Update unit tests to all use the sram_factory

2019-03-06 14:12:24 -08:00

tri_gate.py

Added graph to characterizer to get net names and perform s_en checks. Graph not working with column mux.

2019-05-14 14:44:49 -07:00

wordline_driver.py

Added linear corner factors in analytical delay model.

2019-03-04 00:42:18 -08:00

write_driver_array.py

Added some comments to the spice files.

2019-01-25 15:00:00 -08:00

write_driver.py

Made timing graph more gate-level. Changed edges to be defined by inputs/ouputs and name based.

2019-05-07 00:52:27 -07:00