OpenRAM/compiler
Matt Guthaus 15747b4759 Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev 2018-02-09 10:25:28 -08:00
..
base Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev 2018-02-09 10:25:28 -08:00
characterizer Clean up time statements in openram output 2018-02-08 13:11:18 -08:00
gdsMill Rewrite CONTRIBUTING.md to add changes relative to dev. Add small changes from orbe7947. 2017-12-12 15:50:45 -08:00
modules Organize top-level files into subdirs. 2018-02-09 10:25:24 -08:00
pgates Organize top-level files into subdirs. 2018-02-09 10:25:24 -08:00
router Fix unit tests to be DRC clean. 2017-06-07 10:29:53 -07:00
tests Change argument name for lib in tests as well. 2018-02-08 15:28:49 -08:00
verify Add area/perimeter of source/drain to transistor netlist. Gets rid of some spice warnings, gives better non-annotated measurements. 2018-02-05 16:02:57 -08:00
Makefile Add Makefile for parallel test execution. 2018-01-22 13:39:07 -08:00
debug.py Clean up messages. 2018-01-31 11:54:20 -08:00
example_config_freepdk45.py Fix bug in trim netlist. Add info comments to spice netlist and trimmed netlist. Increase verbosity for simulations. 2018-02-02 19:33:07 -08:00
example_config_scn3me_subm.py Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file. 2018-01-19 16:38:19 -08:00
globals.py Organize top-level files into subdirs. 2018-02-09 10:25:24 -08:00
lef.py Remove metal3 blanket blockage on library cells. 2017-12-19 09:55:59 -08:00
openram.py Reorganize top-level functions a bit more. Add help info to banner. 2018-02-09 09:53:28 -08:00
options.py Add -d option to not delete temp directory on successful runs. 2018-02-01 11:53:02 -08:00
regress.sh Add regress.sh script for convenience 2016-11-18 08:00:34 -08:00
route.py Fix gnd connection in control logic. 2018-02-02 13:04:38 -08:00
sram.py Don't output text in SRAM during unit test. 2018-02-08 14:58:55 -08:00
utils.py Rewrite CONTRIBUTING.md to add changes relative to dev. Add small changes from orbe7947. 2017-12-12 15:50:45 -08:00
verilog.py Revised LEF and Verilog generation. Does not read GDS for speed improvements. 2017-12-19 09:01:24 -08:00