Logo
Explore Help
Sign In
luke/OpenRAM
Watch 1
Star 0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
126d4a8d10f2074f91bdb230f53e226844df717f
OpenRAM/compiler/router
T
History
Matt Guthaus 126d4a8d10 Fix instersection bug. Improve primary and secondary pin algo.
2018-12-04 16:53:04 -08:00
..
tests
Simplifying supply router to single grid track
2018-12-04 08:41:57 -08:00
direction.py
Remove diagonal routing bug. Cleanup.
2018-11-02 14:57:40 -07:00
grid_cell.py
Remove diagonal routing bug. Cleanup.
2018-11-02 14:57:40 -07:00
grid_path.py
Remove diagonal routing bug. Cleanup.
2018-11-02 14:57:40 -07:00
grid_utils.py
Use grid furthest from blockages when blocked pin. Enclose multiple connectors.
2018-11-19 17:32:55 -08:00
grid.py
Supply router working except for off by one rail via error
2018-10-19 14:21:03 -07:00
pin_group.py
Fix instersection bug. Improve primary and secondary pin algo.
2018-12-04 16:53:04 -08:00
router_tech.py
Simplifying supply router to single grid track
2018-12-04 08:41:57 -08:00
router.py
Fix instersection bug. Improve primary and secondary pin algo.
2018-12-04 16:53:04 -08:00
signal_grid.py
Rewrote pin enclosure code to better address off grid pins.
2018-10-10 15:15:58 -07:00
signal_router.py
Change non-preferred route costs.
2018-10-20 14:47:24 -07:00
supply_grid.py
Supply router working except:
2018-09-18 12:57:39 -07:00
supply_router.py
Expand grids to maximal pin before removing blockages
2018-12-04 09:35:40 -08:00
vector3d.py
Use grid furthest from blockages when blocked pin. Enclose multiple connectors.
2018-11-19 17:32:55 -08:00
Powered by Gitea Version: 1.27.2 Page: 247ms Template: 2ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API