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channel_route.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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contact.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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custom_cell_properties.py
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support multi cell wide precharge cells
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2021-04-23 22:49:29 -07:00 |
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custom_layer_properties.py
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fix freepdk45
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2021-06-17 03:21:01 -07:00 |
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delay_data.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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design.py
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add vnb/vpb lvs correspondence points
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2021-06-29 02:31:56 -07:00 |
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errors.py
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Add exception errors file
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2020-04-08 16:55:45 -07:00 |
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geometry.py
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Merge remote-tracking branch 'bvhoof/dev' into dev
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2021-03-01 12:16:26 -08:00 |
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graph_util.py
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Added name changes to on resistance params. Added input capacitance functions to relevant modules for CACTI input load functions.
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2021-07-21 12:24:08 -07:00 |
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hierarchy_design.py
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Add hierarchical seperator option to work with Xyce measurements.
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2021-05-14 16:16:25 -07:00 |
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hierarchy_layout.py
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Make purposes argument to gdsMill. Create prefixGDS.py script.
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2021-06-22 14:40:43 -07:00 |
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hierarchy_spice.py
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Changed CACTI drain cap function to be roughly equivalent but use less parameters. Added drain cap functions to relevant modules. Added drain cap parameters in tech files.
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2021-07-21 14:59:02 -07:00 |
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lef.py
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Improve supply routing for ring and side pins
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2021-05-28 10:58:30 -07:00 |
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pin_layout.py
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fix bias correspondence points
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2021-06-30 05:21:39 -07:00 |
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power_data.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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route.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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utils.py
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fix bias correspondence points
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2021-06-30 05:21:39 -07:00 |
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vector.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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verilog.py
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Fix error in 1 spare column Verilog
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2021-06-21 13:13:53 -07:00 |
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wire.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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wire_path.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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wire_spice_model.py
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Update copyright year.
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2021-01-22 11:23:28 -08:00 |
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