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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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0cc077598efc0eb7457c7150b5a53dcee052d712
OpenRAM/technology/scn3me_subm/gds_lib
T
History
Matt Guthaus 9559421ca8 Connect dff array clk in rows and columns.
2018-02-14 16:46:26 -08:00
..
cell_6t.gds
Add extra pwc to 6T SCMOS cell.
2018-02-05 14:44:15 -08:00
dff.gds
Connect dff array clk in rows and columns.
2018-02-14 16:46:26 -08:00
ms_flop.gds
Add wells to fix DRC errors in SCMOS library cells.
2018-01-22 16:28:20 -08:00
replica_cell_6t.gds
Add extra pwc to 6T SCMOS cell.
2018-02-05 14:44:15 -08:00
sense_amp.gds
Fix devices sizes in SCMOS sense amp. Elaborate magic/netgen scripts in comments.
2018-01-24 13:02:55 -08:00
tri_gate.gds
Fixed bug with missing tri gate via.
2018-01-29 17:29:30 -08:00
write_driver.gds
Fix pin names to lower case. Fix write driver DRC errors and LVS error.
2018-01-31 17:37:16 -08:00
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