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luke
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OpenRAM
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https://github.com/VLSIDA/OpenRAM.git
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0bb41b8a5df2d48ecc8836aee43b86b367535611
OpenRAM
/
technology
/
scn4m_subm
/
sp_lib
T
History
mrg
0fbfa924f7
Add other SCMOS dummy cells
2019-07-03 14:28:12 -07:00
..
cell_1rw_1r.sp
…
cell_1w_1r.sp
Copy 1rw/1r cell to 1w/1r.
2019-02-24 09:54:45 -08:00
cell_6t.sp
…
cell_6t.st0
Copy 1rw/1r cell to 1w/1r.
2019-02-24 09:54:45 -08:00
dff.sp
…
dummy_cell_1rw_1r.sp
Add other SCMOS dummy cells
2019-07-03 14:28:12 -07:00
dummy_cell_1w_1r.sp
Add other SCMOS dummy cells
2019-07-03 14:28:12 -07:00
dummy_cell_6t.sp
Fix dummy row LVS issue
2019-06-14 15:06:04 -07:00
replica_cell_1rw_1r.sp
…
replica_cell_1w_1r.sp
Copy 1rw/1r cell to 1w/1r.
2019-02-24 09:54:45 -08:00
replica_cell_6t.sp
…
sense_amp.sp
…
tri_gate.sp
…
write_driver.sp
…
