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base
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Update router to work with pin_layout structure.
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2018-08-29 15:34:45 -07:00 |
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characterizer
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Remove OEB signal since we split DIN/DOUT ports
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2018-08-13 14:09:49 -07:00 |
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gdsMill
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Update router to work with pin_layout structure.
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2018-08-29 15:34:45 -07:00 |
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modules
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Initial refactor of signal and supply router classes.
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2018-08-29 15:34:45 -07:00 |
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pgates
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Clean up new code for add_modules, add_pins and netlist/layouts.
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2018-08-28 10:24:09 -07:00 |
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router
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Rename _new cell back to original for LVS comparison script
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2018-08-29 15:34:45 -07:00 |
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tests
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Remove extraneous files
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2018-08-29 15:34:45 -07:00 |
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verify
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Rename _new cell back to original for LVS comparison script
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2018-08-29 15:34:45 -07:00 |
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Makefile
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Add Makefile for parallel test execution.
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2018-01-22 13:39:07 -08:00 |
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debug.py
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Output debug warnings and errors to stderr. Clean up regress script a bit.
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2018-07-11 09:51:28 -07:00 |
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example_config_freepdk45.py
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Clean up new code for add_modules, add_pins and netlist/layouts.
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2018-08-28 10:24:09 -07:00 |
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example_config_scn3me_subm.py
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Clean up new code for add_modules, add_pins and netlist/layouts.
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2018-08-28 10:24:09 -07:00 |
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gen_stimulus.py
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Convert entire OpenRAM to use python3. Works with Python 3.6.
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2018-05-14 16:15:45 -07:00 |
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globals.py
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Add sketch for power grid routing code
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2018-08-29 15:34:16 -07:00 |
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openram.py
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Added netlist only configuration option.
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2018-08-27 14:33:02 -07:00 |
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options.py
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Add parameters to give preference to DRC/LVS/PEX tools like we do for spice.
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2018-08-28 13:41:26 -07:00 |
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sram.py
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Converted all modules to not run create_layout when netlist_only
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2018-08-27 16:42:48 -07:00 |
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sram_1bank.py
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Add sketch for power grid routing code
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2018-08-29 15:34:16 -07:00 |
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sram_2bank.py
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Add LVS correspondence points to each bank type
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2018-07-18 14:29:04 -07:00 |
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sram_4bank.py
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Add LVS correspondence points to each bank type
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2018-07-18 14:29:04 -07:00 |
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sram_base.py
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Move place function to instance class rather than hierarchy.
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2018-08-27 17:25:39 -07:00 |
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