mrg 2711093442 Improve signal debug output

2021-07-01 12:47:17 -07:00

..

__init__.py

Merge branch 'dev' into automated_analytical_model

2021-06-09 15:45:41 -07:00

analytical_util.py

Adjusted model prediction to account for a single datafile. Adjusted unscaling data as well.

2021-05-24 12:53:51 -07:00

bit_polarity.py

Update copyright year.

2021-01-22 11:23:28 -08:00

charutils.py

Xyce can be capital or lower case

2021-05-21 12:04:26 -07:00

delay.py

Added a graph exclusion clear for the mux to prevent previous graph creations causing bugs.

2021-06-14 14:39:54 -07:00

elmore.py

Added sim data for freepdk45 and removed stale data

2021-05-26 18:40:46 -07:00

functional.py

Improve signal debug output

2021-07-01 12:47:17 -07:00

lib.py

Changed neural network model to be sklearn based

2021-06-07 12:26:45 -07:00

linear_regression.py

Added functions for testing accuracy of current regression model and associated test.

2021-06-04 15:04:52 -07:00

logical_effort.py

Update copyright year.

2021-01-22 11:23:28 -08:00

measurements.py

Add hierarchical seperator option to work with Xyce measurements.

2021-05-14 16:16:25 -07:00

model_check.py

Add hierarchical seperator option to work with Xyce measurements.

2021-05-14 16:16:25 -07:00

neural_network.py

Changed neural network model to be sklearn based

2021-06-07 12:26:45 -07:00

regression_model.py

Changed the regression test to only run models for the output being tested.

2021-06-16 23:50:20 -07:00

setup_hold.py

Initial Xyce support.

2021-05-14 11:28:29 -07:00

simulation.py

Improve signal debug output

2021-07-01 12:47:17 -07:00

sram_op.py

Update copyright year.

2021-01-22 11:23:28 -08:00

stimuli.py

Edits to functional simulation.

2021-07-01 09:59:13 -07:00

trim_spice.py

Reimplement trim options (except on unit tests).

2021-04-07 16:07:56 -07:00