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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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009f6e94ea6f958ff64fd6fbb7b1ba3ce9f33f4d
OpenRAM/technology/scn3me_subm/sp_lib
T
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Matt Guthaus 58e41a998f Replace write driver with human readable sp file.
2018-11-27 11:49:08 -08:00
..
cell_6t.sp
Change internal nets of 6T cell and write driver to have useful names for debugging.
2018-07-26 11:26:47 -07:00
dff.sp
Remove ms_flop and replace with dff. Might break setup_hold tests.
2018-09-13 11:02:28 -07:00
ms_flop.sp
Get rid of netgen error of undefined dlatch. Fix sp_read to find correct subckt name and pins.
2018-02-27 08:59:46 -08:00
replica_cell_6t.sp
RELEASE 1.0
2016-11-08 09:57:35 -08:00
sense_amp.sp
Fix pin nameon sense amp spice. Fix NAND2 bug in hierarchical decoder.
2018-02-02 14:08:56 -08:00
tri_gate.sp
RELEASE 1.0
2016-11-08 09:57:35 -08:00
write_driver.sp
Replace write driver with human readable sp file.
2018-11-27 11:49:08 -08:00
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